Summary ALU, CPU, Registers and buses - SLR 1 OCR ALEVEL COMP SCI

Topic: ALU, CU, registers and buses


Questions Notes




Control unit
 Coordinates all activities of the CPU
 Directs flow of data between CPU and other devices
 Fetches next instruction, decodes it, executes it, stores the resulting
data back in memory or registers
 Sends memory read and write request to main memory on the control
bus – and other command and control signals such as bus requests, bus
grants, interrupt requests
 Makes extensive use of status registers and clock
 Coordinates and communicates with all parts of the CPU (orange lines)

Program counter
 Holds the address of the next instruction to be executed
 This could be:
o Next instruction in a sequence of instructions
o Address to jump to if the current instruction is a command to
jump or a branch – this would be copied from the current
instruction register
 Close relationship with MAR (Memory address register) - At start of
every fetch,decode,execute cycle, the address held in PC Is copied to
MAR.

Memory address register (MAR)
 Holds address of memory location from which:
o Data
o Instruction