OutLearn The Characteristics of Contemporary P
Structure and Function
1 Structure and Function of a Processor
of a Processor
What is the function of
2 Carries out the instructions in computer programs
a CPU?
3 What is a CPU? Central Processing Unit
Arithmetic Logic Unit
What are the main
4 Control Unit
components of a CPU?
Registers
How are components
5 on a CPU connected Buses
together?
What is the function of Carries out the calculations and logical decisions
6
the ALU? Results of these calculations are stored in the ACC
Coordinates how the processor works
What is the function of Controls how data moves around parts of the CPU
7
the CU? Controls how data moves between the CPU and memory
Instructions are decoded in the CU
What is the function of Areas of memory within the processor itself
8
registers? Accessed at extremely fast speeds to be used without bottleneck
Holds the address of the next instruction to be executed
Function of the
9 Incremented to point to the next instruction
Program Counter?
BRA/BRP/BRZ
Function of the
Stores the address of the data or instructions that are to be fetched from or sent t
10 Memory Address
memory
Register?
Function of the
11 Stores the data or instructions that are to be fetched from or sent to memory
Memory Data Register?
Function of the
12 Current Instruction Stores the most recently fetched instruction, which will be decoded and executed
Register?
Function of the
13 Stores the result of calculations made by the ALU
Accumulator?
Function of general
14 Temporarily store data being used rather than sending data to and from memory
purpose registers?
15 What is a bus? Communication channels through which data can be sent around the computer
1. Address bus carries the address of the memory location being read from or
written to
What are the three bus
16
rules? 2. Data bus carries data between the processor and memory
3. Control bus sends control signals from the control unit
, What is the
17 fetch-decode-execute Processor works by continually fetching, decoding and then executing instructions
cycle?
1) Contents of PC copied to MAR
2.1) Read signal sent by CU across control bus
What are the steps for 2.2) Contents of of MAR sent across address bus
18 the fetch part of the
FDE cycle? 3) Contents at MAR location sent to MDR across data bus
4) Contents of MDR copied to CIR
5) PC incremented by 1
What are the steps for 6) Contents of CIR sent to CU
19 the decode part of the
FDE cycle? 7) CU decodes next instruction
Case 1 - STA/LDA:
- Read/write location sent to MAR
What are the steps for - FDE cycle carried out
20 the execute part of the
FDE cycle? Case 2 - ADD/SUB:
- Contents of MDR and ACC sent to ALU
- Result sent back to the ACC
- Clock Speed
What factors affect the - Number of cores
21 performance of the
CPU? - Amount of cache memory
- Use of pipelining
How does clock speed The higher the clock speed, the more pulses per second that the CPU can produce
22 affect the
performance? More instructions can be executed per second
Core is a processing unit within the CPU
- Each core is a distinct, independent processing unit
How does the number
23 of cores affect the - Different cores can run different applications (multi-tasking)
performance? - Multiple cores can also work on the same application
- More cores = tasks that can be shared will run more quickly
Random Access Memory is significantly slower than the speed the CPU operates at
To compensate, processors have a small amount of fast memory called cache
memory:
- Temporary store
How does the cache - Built into processor, reducing distance travelled
24 affect the
- Data and instructions regularly accessed are kept in cache
performance?
- Speed less likely to be limited by RAM's access speed
- L1 cache = smallest & fastest
- Subsequent levels faster, larger, further away from centre
- Modern CPUs have 3 to 4 levels of cache
Processor starvation is an issue, parts left idling
How does pipelining
Different parts of the CPU can perform different parts of the FDE cycle on a sequence
25 affect the
of instructions
performance?
One executed, one after decoded, one after that fetched
, Only works when next instruction can be predicted
What are the issues I.e. branch instruction causes issues - CPU may not predict the next instruction
26
with pipelining? correctly
Pipeline has to be cleared - takes time
Single CU
Single ALU
What is a Von
27 Single memory store that contains both instructions and data
Neumann architecture?
-Disadvantage; can hold up FDE
-Not possible to read & write data at the same time
What is a Harvard Separate memory units & buses for data and instructions
28
architecture? -Doesn't suffer from the restriction of a single memory store
Simultaneous Multi-threading
Out of order execution
What are features of a
29 contemporary Branch Prediction
processors? Variable Clock Speed
Power Conservation
- A 'thread' is a sequence of instructions that are to be processed
What is simultaneous - 'Front-end' is duplicated, capable of fetching and decoding two threads at once
30
multi-threading? - Execution part of CPU can switch between two threads
- Cannot outperform two separate cores
Allows instructions to be executed ahead of time
What is out of order
31 - Prevents processor starvation and hence, delays
execution?
- Requires CPU to check instruction isn't dependent on the ones prior
Modern CPUs can use branch prediction to try and work out where a program will go
What is branch at a decision point
32
prediction?
- Reduces how often the pipeline needs to be cleared
Modern processors can change their clock speed
What is variable clock - Temporarily increase it; small performance boost
33
speed? - Time limit due to overheating
- Clock speed can also be reduced for reduced power consumption
Modern CPUs can shut off parts of their circuitry
What is power
34 i.e. dedicated video processing
conservation?
Discrete GPU can be powered off until it is needed
35 Types of Processor Types of Processor
A reduced instruction set computing processor
- Small range of instructions
What is a RISC - Low power; fewer transistors
36
processor? - Compiler does more work
- Single clock cycle
- Fewer addressing modes
Structure and Function
1 Structure and Function of a Processor
of a Processor
What is the function of
2 Carries out the instructions in computer programs
a CPU?
3 What is a CPU? Central Processing Unit
Arithmetic Logic Unit
What are the main
4 Control Unit
components of a CPU?
Registers
How are components
5 on a CPU connected Buses
together?
What is the function of Carries out the calculations and logical decisions
6
the ALU? Results of these calculations are stored in the ACC
Coordinates how the processor works
What is the function of Controls how data moves around parts of the CPU
7
the CU? Controls how data moves between the CPU and memory
Instructions are decoded in the CU
What is the function of Areas of memory within the processor itself
8
registers? Accessed at extremely fast speeds to be used without bottleneck
Holds the address of the next instruction to be executed
Function of the
9 Incremented to point to the next instruction
Program Counter?
BRA/BRP/BRZ
Function of the
Stores the address of the data or instructions that are to be fetched from or sent t
10 Memory Address
memory
Register?
Function of the
11 Stores the data or instructions that are to be fetched from or sent to memory
Memory Data Register?
Function of the
12 Current Instruction Stores the most recently fetched instruction, which will be decoded and executed
Register?
Function of the
13 Stores the result of calculations made by the ALU
Accumulator?
Function of general
14 Temporarily store data being used rather than sending data to and from memory
purpose registers?
15 What is a bus? Communication channels through which data can be sent around the computer
1. Address bus carries the address of the memory location being read from or
written to
What are the three bus
16
rules? 2. Data bus carries data between the processor and memory
3. Control bus sends control signals from the control unit
, What is the
17 fetch-decode-execute Processor works by continually fetching, decoding and then executing instructions
cycle?
1) Contents of PC copied to MAR
2.1) Read signal sent by CU across control bus
What are the steps for 2.2) Contents of of MAR sent across address bus
18 the fetch part of the
FDE cycle? 3) Contents at MAR location sent to MDR across data bus
4) Contents of MDR copied to CIR
5) PC incremented by 1
What are the steps for 6) Contents of CIR sent to CU
19 the decode part of the
FDE cycle? 7) CU decodes next instruction
Case 1 - STA/LDA:
- Read/write location sent to MAR
What are the steps for - FDE cycle carried out
20 the execute part of the
FDE cycle? Case 2 - ADD/SUB:
- Contents of MDR and ACC sent to ALU
- Result sent back to the ACC
- Clock Speed
What factors affect the - Number of cores
21 performance of the
CPU? - Amount of cache memory
- Use of pipelining
How does clock speed The higher the clock speed, the more pulses per second that the CPU can produce
22 affect the
performance? More instructions can be executed per second
Core is a processing unit within the CPU
- Each core is a distinct, independent processing unit
How does the number
23 of cores affect the - Different cores can run different applications (multi-tasking)
performance? - Multiple cores can also work on the same application
- More cores = tasks that can be shared will run more quickly
Random Access Memory is significantly slower than the speed the CPU operates at
To compensate, processors have a small amount of fast memory called cache
memory:
- Temporary store
How does the cache - Built into processor, reducing distance travelled
24 affect the
- Data and instructions regularly accessed are kept in cache
performance?
- Speed less likely to be limited by RAM's access speed
- L1 cache = smallest & fastest
- Subsequent levels faster, larger, further away from centre
- Modern CPUs have 3 to 4 levels of cache
Processor starvation is an issue, parts left idling
How does pipelining
Different parts of the CPU can perform different parts of the FDE cycle on a sequence
25 affect the
of instructions
performance?
One executed, one after decoded, one after that fetched
, Only works when next instruction can be predicted
What are the issues I.e. branch instruction causes issues - CPU may not predict the next instruction
26
with pipelining? correctly
Pipeline has to be cleared - takes time
Single CU
Single ALU
What is a Von
27 Single memory store that contains both instructions and data
Neumann architecture?
-Disadvantage; can hold up FDE
-Not possible to read & write data at the same time
What is a Harvard Separate memory units & buses for data and instructions
28
architecture? -Doesn't suffer from the restriction of a single memory store
Simultaneous Multi-threading
Out of order execution
What are features of a
29 contemporary Branch Prediction
processors? Variable Clock Speed
Power Conservation
- A 'thread' is a sequence of instructions that are to be processed
What is simultaneous - 'Front-end' is duplicated, capable of fetching and decoding two threads at once
30
multi-threading? - Execution part of CPU can switch between two threads
- Cannot outperform two separate cores
Allows instructions to be executed ahead of time
What is out of order
31 - Prevents processor starvation and hence, delays
execution?
- Requires CPU to check instruction isn't dependent on the ones prior
Modern CPUs can use branch prediction to try and work out where a program will go
What is branch at a decision point
32
prediction?
- Reduces how often the pipeline needs to be cleared
Modern processors can change their clock speed
What is variable clock - Temporarily increase it; small performance boost
33
speed? - Time limit due to overheating
- Clock speed can also be reduced for reduced power consumption
Modern CPUs can shut off parts of their circuitry
What is power
34 i.e. dedicated video processing
conservation?
Discrete GPU can be powered off until it is needed
35 Types of Processor Types of Processor
A reduced instruction set computing processor
- Small range of instructions
What is a RISC - Low power; fewer transistors
36
processor? - Compiler does more work
- Single clock cycle
- Fewer addressing modes
