Department of Electrical Engineering
Faculty Member:____________________ Dated: ________________
Semester:__________________________ Section: ________________
Group No.:
EE-221: Digital Logic Design
Lab 5: Binary to Gray and Gray to Binary Code Conversion
PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7
Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performanc of data in Tool Usage Safety and Team marks
e Lab Report Work Obtained
5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks
EE-221: Digital Logic Design Page 1
, Lab5: Part (a): Binary to Gray and Gray to Binary Code Conversion
Lab5: Part (b): Gate-level Modeling in Verilog
Lab Instructions
This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session.
The lab report will be uploaded on LMS three days before scheduled lab date. The students will get
hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it with
teacher/lab engineer for necessary evaluation. Alternately each group to upload completed lab
report on LMS for grading.
The students will start lab task and demonstrate design steps separately for step-wise
evaluation( course instructor/lab engineer will sign each step after ascertaining functional
verification)
Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will
simplify trouble-shooting process.
After the lab, students are expected to unwire the circuit and deposit back components before
leaving.
The students will complete lab task and submit complete report to Lab Engineer before leaving
lab.
The Total duration for the lab is 3 hrs. After lab duration, a deduction of 5 marks per day
will be done for late submission.
A lab with in-complete lab tasks will not be accepted.
There are related questions at the end of this activity. Give complete answers.
EE-221: Digital Logic Design Page 2
Faculty Member:____________________ Dated: ________________
Semester:__________________________ Section: ________________
Group No.:
EE-221: Digital Logic Design
Lab 5: Binary to Gray and Gray to Binary Code Conversion
PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7
Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performanc of data in Tool Usage Safety and Team marks
e Lab Report Work Obtained
5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks
EE-221: Digital Logic Design Page 1
, Lab5: Part (a): Binary to Gray and Gray to Binary Code Conversion
Lab5: Part (b): Gate-level Modeling in Verilog
Lab Instructions
This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session.
The lab report will be uploaded on LMS three days before scheduled lab date. The students will get
hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it with
teacher/lab engineer for necessary evaluation. Alternately each group to upload completed lab
report on LMS for grading.
The students will start lab task and demonstrate design steps separately for step-wise
evaluation( course instructor/lab engineer will sign each step after ascertaining functional
verification)
Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will
simplify trouble-shooting process.
After the lab, students are expected to unwire the circuit and deposit back components before
leaving.
The students will complete lab task and submit complete report to Lab Engineer before leaving
lab.
The Total duration for the lab is 3 hrs. After lab duration, a deduction of 5 marks per day
will be done for late submission.
A lab with in-complete lab tasks will not be accepted.
There are related questions at the end of this activity. Give complete answers.
EE-221: Digital Logic Design Page 2
