QUIZ 2 PLC QUESTIONS WITH VERIFIED SOLUTIONS LATEST UPDATE 2026
True or False
All inputs to a NAND gate must be 1 to produce a 1 output. - Answers False
The basic rule for an OR gate is
-If one or more inputs are 1, the output is 1.
-If one or more inputs are 1, output is 0.
-If one or more inputs are 0, the output is 1.
-Both B and C - Answers If one or more inputs are 1, the output is 1.
The logic function(s) used by PI-C's is (are):
-NOT
-AND
-all of these.
-OR - Answers all of these
A single rung of a ladder logic program is arranged with:
-Input conditions connected from left to right, with the output at the far right.
-Input conditions connected from right to left, with the output at the far left
-The output in the center and the input conditions to the left and right of it.
-All input conditions in parallel and all output conditions in series. - Answers Input conditions
connected from left to right, with the output at the far right.
The binary concept used in logic refers to the fact that many things can be thought of as existing
in
one of ___ states. - Answers two
True or False
, Hardwired logic is changeable only by altering the way devices are connected - Answers True
Which of the following gates is commonly used for the comparison of two binary numbers?
-NOT
-XOR
-NAND
-NOR - Answers XOR
The NOT function is also called a(an) ____. - Answers Inverter
The logic function(s) used by PIC's is (are):
-OR
-all or these
-NOT
-AND - Answers all of these
True or False
Ladder logic is a graphical representation of a user program - Answers True
The mathematical study of the binary number system and logic is called _____ algebra -
Answers Boolean
True or False
With an AND gate, if any input is 0, the output will be 0. - Answers True
True or False
A two input OR function, expressed as a Boolean equation, would be Y=AB. - Answers False
True or False
Inverting the output of an Or gate will result in creating a NOR gate - Answers True
The NOT output is 1 if the input is ____. - Answers zero
The ______ table shows the resulting output for each possible gate input conditions.
True or False
All inputs to a NAND gate must be 1 to produce a 1 output. - Answers False
The basic rule for an OR gate is
-If one or more inputs are 1, the output is 1.
-If one or more inputs are 1, output is 0.
-If one or more inputs are 0, the output is 1.
-Both B and C - Answers If one or more inputs are 1, the output is 1.
The logic function(s) used by PI-C's is (are):
-NOT
-AND
-all of these.
-OR - Answers all of these
A single rung of a ladder logic program is arranged with:
-Input conditions connected from left to right, with the output at the far right.
-Input conditions connected from right to left, with the output at the far left
-The output in the center and the input conditions to the left and right of it.
-All input conditions in parallel and all output conditions in series. - Answers Input conditions
connected from left to right, with the output at the far right.
The binary concept used in logic refers to the fact that many things can be thought of as existing
in
one of ___ states. - Answers two
True or False
, Hardwired logic is changeable only by altering the way devices are connected - Answers True
Which of the following gates is commonly used for the comparison of two binary numbers?
-NOT
-XOR
-NAND
-NOR - Answers XOR
The NOT function is also called a(an) ____. - Answers Inverter
The logic function(s) used by PIC's is (are):
-OR
-all or these
-NOT
-AND - Answers all of these
True or False
Ladder logic is a graphical representation of a user program - Answers True
The mathematical study of the binary number system and logic is called _____ algebra -
Answers Boolean
True or False
With an AND gate, if any input is 0, the output will be 0. - Answers True
True or False
A two input OR function, expressed as a Boolean equation, would be Y=AB. - Answers False
True or False
Inverting the output of an Or gate will result in creating a NOR gate - Answers True
The NOT output is 1 if the input is ____. - Answers zero
The ______ table shows the resulting output for each possible gate input conditions.
