EEE 120
Digital Design Fundamentals
MIDTERM READINESS EXAM
GUIDE
Q&S
©2024/2025
,1. Multiple Choice: What is the primary function of a
Karnaugh map in digital design?
a) To optimize Boolean functions
b) To convert binary to hexadecimal
c) To design circuit layouts
d) To simulate digital circuits
Correct Answer: a) To optimize Boolean functions
Rationale: Karnaugh maps are used for simplifying
Boolean algebra expressions, which helps in the
optimization of logic circuits.
2. Fill-in-the-Blank: The process of converting a sequential
circuit into a combinational circuit is known as _______.
Correct Answer: State reduction
Rationale: State reduction is the process of simplifying the
state machine by reducing the number of states while
maintaining the same functionality.
3. True/False: In digital design, asynchronous circuits are
considered safer and more reliable than synchronous
circuits.
Correct Answer: False
Rationale: Asynchronous circuits do not rely on a global
clock and can be faster, but they are generally considered
less reliable due to issues like metastability.
4. Multiple Response: Which of the following are
advantages of using VHDL for digital design? (Select all
that apply)
a) Portability
b) Readability
©2024/2025
, c) Simplicity
d) Scalability
Correct Answers: a) Portability, b) Readability, d)
Scalability
Rationale: VHDL allows for the design of portable,
readable, and scalable digital circuits, though it is not
necessarily simple.
5. Multiple Choice: Which type of logic gate is represented
by the following truth table?
| A | B | Output |
|---|---|--------|
|0|0|1 |
|0|1|1 |
|1|0|1 |
|1|1|0 |
a) AND
b) OR
c) NAND
d) NOR
Correct Answer: c) NAND
Rationale: The NAND gate produces an output which is
false only when all its inputs are true.
6. Fill-in-the-Blank: _______ is a common technique used
to minimize the risk of timing errors in flip-flops.
Correct Answer: Edge triggering
Rationale: Edge triggering ensures that the state of the
flip-flop changes only at the edge of the clock signal,
reducing the risk of timing errors.
7. True/False: A multiplexer can be used to implement any
Boolean function.
©2024/2025
Digital Design Fundamentals
MIDTERM READINESS EXAM
GUIDE
Q&S
©2024/2025
,1. Multiple Choice: What is the primary function of a
Karnaugh map in digital design?
a) To optimize Boolean functions
b) To convert binary to hexadecimal
c) To design circuit layouts
d) To simulate digital circuits
Correct Answer: a) To optimize Boolean functions
Rationale: Karnaugh maps are used for simplifying
Boolean algebra expressions, which helps in the
optimization of logic circuits.
2. Fill-in-the-Blank: The process of converting a sequential
circuit into a combinational circuit is known as _______.
Correct Answer: State reduction
Rationale: State reduction is the process of simplifying the
state machine by reducing the number of states while
maintaining the same functionality.
3. True/False: In digital design, asynchronous circuits are
considered safer and more reliable than synchronous
circuits.
Correct Answer: False
Rationale: Asynchronous circuits do not rely on a global
clock and can be faster, but they are generally considered
less reliable due to issues like metastability.
4. Multiple Response: Which of the following are
advantages of using VHDL for digital design? (Select all
that apply)
a) Portability
b) Readability
©2024/2025
, c) Simplicity
d) Scalability
Correct Answers: a) Portability, b) Readability, d)
Scalability
Rationale: VHDL allows for the design of portable,
readable, and scalable digital circuits, though it is not
necessarily simple.
5. Multiple Choice: Which type of logic gate is represented
by the following truth table?
| A | B | Output |
|---|---|--------|
|0|0|1 |
|0|1|1 |
|1|0|1 |
|1|1|0 |
a) AND
b) OR
c) NAND
d) NOR
Correct Answer: c) NAND
Rationale: The NAND gate produces an output which is
false only when all its inputs are true.
6. Fill-in-the-Blank: _______ is a common technique used
to minimize the risk of timing errors in flip-flops.
Correct Answer: Edge triggering
Rationale: Edge triggering ensures that the state of the
flip-flop changes only at the edge of the clock signal,
reducing the risk of timing errors.
7. True/False: A multiplexer can be used to implement any
Boolean function.
©2024/2025
