1
Important Questions and Answers
CP25201- Multicore Architecture
Syllabus
1. Multicore Systems and Architectures: Evolution from Single-core to Multicore Systems -
SIMD vs MIMD Architectures - Shared and Distributed Memory Systems - Cache
Coherence and Memory Consistency.
Practical:
1. Write a program to create and execute multiple threads using Pthreads.
2. Write a program to demonstrate mutex locks using std::mutex.
2. Thread Management and Synchronization Techniques: Synchronization primitives:
Mutex - Locks - Semaphores - Data races and deadlocks - Inter-thread communication:
Condition variables- Pipes.
Practical:
1. Write a program to compute the Fibonacci series using OpenMP tasks.
2. Write a Rust program to spawn threads and use channels for communication.
3. Parallel Programming using OpenMP for Shared Memory: OpenMP architecture and
memory model - Directives and work-sharing constructs - Parallelizing Loops and Task
Management - Performance optimization.
Practical:
1. Write a program using MPI to calculate the average of an array using collective
communication
es
4. Message Passing Programming with MPI: MPI programming concepts - Point-to-point
ot
and collective communication - Derived data types and synchronization - Performance
N
tuning.
EC
Practical:
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1. Write a program using the threading module to demonstrate data race and synchronization.
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2. Write a program to perform matrix multiplication using OpenMP.
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V.
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5. Evaluating Parallel Performance and Scalability: Measuring and analyzing performance -
Scalability metrics - Use of Profiling Tools for Performance Bottlenecks.
Practical:
1. Write a Rust program to parallelize a for loop using the rayon crate.
2. Write a program and profile its performance using `gprof` or `perf`.
6. Advanced Concepts and Practical Case Studies: Tree search, N-body simulation, graph
algorithms - Comparative Analysis of OpenMP and MPI Implementations - Trends in
multicore and manycore processors.
Practical:
1.Mini Project: Write a C program to implement parallel merge sort or breadth-first search
using both OpenMP and MPI.Compare complexity.
S.No. Description
Unit-I
Multicore Systems and Architectures
Basic Concepts
S.
Basic Concept Definition / Important Points
No.
A processor with one CPU core that executes one instruction stream at a time.
1 Single-core System Performance improvement mainly depends on clock speed and instruction
efficiency.
A processor containing two or more cores on a single chip. It improves
2 Multicore System
parallel processing, throughput, and energy efficiency.
Increasing clock speeds causes higher power consumption and heat.
Evolution: Single-
3 Multicore processors improve performance by executing multiple tasks in
core to Multicore
parallel.
Single Instruction, Multiple Data. One instruction operates on multiple data
4 SIMD Architecture elements simultaneously. Used in graphics, image processing, and vector
operations.
Multiple Instruction, Multiple Data. Different processors execute different
MIMD
5 instructions on different data independently. Used in multicore CPUs and
Architecture
multiprocessor systems.
es
All processors access a common memory space. Communication is easy
Shared Memory
ot
6 through shared variables, but synchronization and cache coherence are
N
System
important.
EC
Distributed Each processor has its own local memory. Processors communicate by
./
7
of
Memory System message passing. It offers scalability but requires explicit communication.
Pr
Ensures that multiple cached copies of the same memory location remain
8 Cache Coherence
,
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consistent. Common protocols include MSI, MESI, and MOESI.
at
ap
m
U
V.
, 3
Defines the order in which memory operations become visible to different
Memory
9 processors. Sequential consistency requires a result equivalent to some single
Consistency
sequential order that preserves each processor's program order.
Measures the performance gain from parallel execution compared with
10 Parallel Speedup
sequential execution.
Important equations (copy to Word)
1. Parallel Speedup
Speedup (S) = Sequential Execution Time / Parallel Execution Time
S = T1 / Tp
2. Parallel Efficiency
Efficiency (E) = Speedup / Number of Processors
E=S/P
3. Amdahl’s Law
S(P) = 1 / [(1 − f) + (f / P)]
Where f = parallelizable fraction of the program and P = number of processors.
4. Ideal Parallel Execution Time
Tp = T1 / P
(Assumes perfect parallelism with no communication or synchronization overhead.)
Key exam point
es
SIMD: One instruction operates on multiple data items.
ot
N
MIMD: Multiple processors execute different instructions independently.
EC
Cache coherence: Maintains consistent cached data.
./
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Memory consistency: Defines the observable ordering of memory operations.
,Pr
Multiple Choice QA
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V.
, 4
1. What is the main advantage of a multicore processor over a single-core processor?
A) Reduced number of instructions
B) Improved parallel processing
C) Elimination of cache memory
D) Reduced instruction set
Answer: B) Improved parallel processing
Reason: A multicore processor contains two or more processing cores on a single chip. These cores
can execute multiple tasks or threads simultaneously, improving performance and throughput.
Equation (plain text):
Speedup (S) = Execution time on 1 core / Execution time on N cores
2. Which architecture executes the same instruction on multiple data elements simultaneously?
A) SISD
B) SIMD
C) MISD
D) MIMD
Answer: B) SIMD
Reason: SIMD stands for Single Instruction, Multiple Data. It is useful for vector operations, image
processing, scientific computing, and graphics processing.
Equation (plain text):
es
ot
C[i] = A[i] + B[i], for i = 1, 2, ..., n
N
EC
3. Which statement correctly describes a shared-memory multiprocessor system?
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of
A) Each processor has a completely separate address space
Pr
,
hy
at
ap
m
U
V.
Important Questions and Answers
CP25201- Multicore Architecture
Syllabus
1. Multicore Systems and Architectures: Evolution from Single-core to Multicore Systems -
SIMD vs MIMD Architectures - Shared and Distributed Memory Systems - Cache
Coherence and Memory Consistency.
Practical:
1. Write a program to create and execute multiple threads using Pthreads.
2. Write a program to demonstrate mutex locks using std::mutex.
2. Thread Management and Synchronization Techniques: Synchronization primitives:
Mutex - Locks - Semaphores - Data races and deadlocks - Inter-thread communication:
Condition variables- Pipes.
Practical:
1. Write a program to compute the Fibonacci series using OpenMP tasks.
2. Write a Rust program to spawn threads and use channels for communication.
3. Parallel Programming using OpenMP for Shared Memory: OpenMP architecture and
memory model - Directives and work-sharing constructs - Parallelizing Loops and Task
Management - Performance optimization.
Practical:
1. Write a program using MPI to calculate the average of an array using collective
communication
es
4. Message Passing Programming with MPI: MPI programming concepts - Point-to-point
ot
and collective communication - Derived data types and synchronization - Performance
N
tuning.
EC
Practical:
./
of
1. Write a program using the threading module to demonstrate data race and synchronization.
Pr
2. Write a program to perform matrix multiplication using OpenMP.
,
hy
at
ap
m
U
V.
, 2
5. Evaluating Parallel Performance and Scalability: Measuring and analyzing performance -
Scalability metrics - Use of Profiling Tools for Performance Bottlenecks.
Practical:
1. Write a Rust program to parallelize a for loop using the rayon crate.
2. Write a program and profile its performance using `gprof` or `perf`.
6. Advanced Concepts and Practical Case Studies: Tree search, N-body simulation, graph
algorithms - Comparative Analysis of OpenMP and MPI Implementations - Trends in
multicore and manycore processors.
Practical:
1.Mini Project: Write a C program to implement parallel merge sort or breadth-first search
using both OpenMP and MPI.Compare complexity.
S.No. Description
Unit-I
Multicore Systems and Architectures
Basic Concepts
S.
Basic Concept Definition / Important Points
No.
A processor with one CPU core that executes one instruction stream at a time.
1 Single-core System Performance improvement mainly depends on clock speed and instruction
efficiency.
A processor containing two or more cores on a single chip. It improves
2 Multicore System
parallel processing, throughput, and energy efficiency.
Increasing clock speeds causes higher power consumption and heat.
Evolution: Single-
3 Multicore processors improve performance by executing multiple tasks in
core to Multicore
parallel.
Single Instruction, Multiple Data. One instruction operates on multiple data
4 SIMD Architecture elements simultaneously. Used in graphics, image processing, and vector
operations.
Multiple Instruction, Multiple Data. Different processors execute different
MIMD
5 instructions on different data independently. Used in multicore CPUs and
Architecture
multiprocessor systems.
es
All processors access a common memory space. Communication is easy
Shared Memory
ot
6 through shared variables, but synchronization and cache coherence are
N
System
important.
EC
Distributed Each processor has its own local memory. Processors communicate by
./
7
of
Memory System message passing. It offers scalability but requires explicit communication.
Pr
Ensures that multiple cached copies of the same memory location remain
8 Cache Coherence
,
hy
consistent. Common protocols include MSI, MESI, and MOESI.
at
ap
m
U
V.
, 3
Defines the order in which memory operations become visible to different
Memory
9 processors. Sequential consistency requires a result equivalent to some single
Consistency
sequential order that preserves each processor's program order.
Measures the performance gain from parallel execution compared with
10 Parallel Speedup
sequential execution.
Important equations (copy to Word)
1. Parallel Speedup
Speedup (S) = Sequential Execution Time / Parallel Execution Time
S = T1 / Tp
2. Parallel Efficiency
Efficiency (E) = Speedup / Number of Processors
E=S/P
3. Amdahl’s Law
S(P) = 1 / [(1 − f) + (f / P)]
Where f = parallelizable fraction of the program and P = number of processors.
4. Ideal Parallel Execution Time
Tp = T1 / P
(Assumes perfect parallelism with no communication or synchronization overhead.)
Key exam point
es
SIMD: One instruction operates on multiple data items.
ot
N
MIMD: Multiple processors execute different instructions independently.
EC
Cache coherence: Maintains consistent cached data.
./
of
Memory consistency: Defines the observable ordering of memory operations.
,Pr
Multiple Choice QA
hy
at
ap
m
U
V.
, 4
1. What is the main advantage of a multicore processor over a single-core processor?
A) Reduced number of instructions
B) Improved parallel processing
C) Elimination of cache memory
D) Reduced instruction set
Answer: B) Improved parallel processing
Reason: A multicore processor contains two or more processing cores on a single chip. These cores
can execute multiple tasks or threads simultaneously, improving performance and throughput.
Equation (plain text):
Speedup (S) = Execution time on 1 core / Execution time on N cores
2. Which architecture executes the same instruction on multiple data elements simultaneously?
A) SISD
B) SIMD
C) MISD
D) MIMD
Answer: B) SIMD
Reason: SIMD stands for Single Instruction, Multiple Data. It is useful for vector operations, image
processing, scientific computing, and graphics processing.
Equation (plain text):
es
ot
C[i] = A[i] + B[i], for i = 1, 2, ..., n
N
EC
3. Which statement correctly describes a shared-memory multiprocessor system?
./
of
A) Each processor has a completely separate address space
Pr
,
hy
at
ap
m
U
V.
