CAMBRIDGE IGCSE® COMPUTER SCIENCE (2210 /
0478)
CHAPTER 3: HARDWARE — COMPREHENSIVE STUDY & REVISION GUIDE
Syllabus Reference: Section 3.1 - 3.4 Target Grades: A* / Grade 9 Specialist Notes
Topic: Computer Architecture, Input/Output, Storage & Network Format: High-Yield Revision Summary for Stuvia
Hardware Sales
This study guide covers the entire Chapter 3 specification for Cambridge IGCSE Computer Science ().
Designed to meet exam mark schemes, it features Von Neumann architecture, Fetch-Decode-Execute cycles, sensors,
primary/secondary/target storage technologies, and network devices.
1. COMPUTER ARCHITECTURE & THE CPU
1.1 Von Neumann Architecture
The Von Neumann architecture is the theoretical design for modern general-purpose electronic computers. Its defining
characteristic is that data and program instructions are stored together in the same shared memory (RAM).
DIAGRAM 3.1: VON NEUMANN CPU ARCHITECTURE & BUS CONNECTIONS
+-----------------------------------------------------------------------+
| CENTRAL PROCESSING UNIT |
| |
| +-----------------------+ +-----------------------+ |
| | CONTROL UNIT (CU) | | ALU (Arithmetic | |
| | | | Logic Unit) | |
| | • Coordinates CPU | | • Arithmetic (+,-) | |
| | • Contains PC & CIR | | • Logical (AND, OR) | |
| +-----------+-----------+ +-----------+-----------+ |
| | | |
| +-------------------+-------------------+ |
| | |
| +-------------------------------+-------------------------------+ |
| | INTERNAL REGISTERS | |
| | • PC (Program Counter) • MAR (Memory Address Reg) | |
| | • CIR (Current Instruction Reg) • MDR (Memory Data Reg) | |
| | • ACC (Accumulator) | |
| +-------------------------------+-------------------------------+ |
+-----------------------------------|-----------------------------------+
|
========================+========================
|| CONTROL BUS (Unidirectional/Bidirect) ||
|| ADDRESS BUS (Unidirectional) ||
|| DATA BUS (Bidirectional) ||
========================+========================
|
+-----------------------------------|-----------------------------------+
| MAIN MEMORY (RAM) |
| |
| [ Address 0x00 ] -> Instruction / Data |
| [ Address 0x01 ] -> Instruction / Data |
+-----------------------------------------------------------------------+
IGCSE Computer Science (2210/0478) - Chapter 3: Hardware Page 1 of 6
, 1.2 CPU Components & Registers
Component / Register Abbr. Detailed Function & Exam Description
Controls signals, synchronizes CPU operations using system clock pulses, and
Control Unit CU
decodes instructions.
Performs mathematical operations (addition, subtraction) and logical comparisons
Arithmetic Logic Unit ALU
(AND, OR, NOT, >, <).
Holds the memory address of the next instruction to be fetched from RAM.
Program Counter PC
Increments automatically.
Memory Address Holds the memory address currently being read from or written to in RAM. Connected
MAR
Register directly to the Address Bus.
Holds the actual data or instruction fetched from memory or awaiting write back.
Memory Data Register MDR
Connected directly to the Data Bus.
Current Instruction
CIR Holds the instruction currently being decoded and executed by the CU.
Register
Temporary register that stores the immediate mathematical or logical results produced
Accumulator ACC
by the ALU.
1.3 System Buses
Bus Name Directionality Function & Purpose
Address Unidirectional (CPU → Carries memory addresses from the MAR to RAM/I-O units. Width determines
Bus Memory) addressable memory capacity.
Bidirectional (CPU ↔ Carries actual data and instructions between CPU registers (MDR) and
Data Bus
Memory) Memory/Peripherals.
Control Bidirectional / Carries control and timing signals (e.g., Read, Write, Interrupt, Clock) across
Bus Unidirectional components.
1.4 The Fetch-Decode-Execute (F-D-E) Cycle
Step-by-Step F-D-E Sequence (Must memorize for 4–6 mark questions):
1. FETCH:
◦ The address of the next instruction in the PC is copied to the MAR.
◦ The PC is incremented by 1 to point to the next instruction.
◦ The instruction stored at the address in MAR is fetched via the Data Bus into the MDR.
◦ The instruction is transferred from the MDR into the CIR.
2. DECODE:
◦ The Control Unit (CU) decodes the instruction in the CIR to determine opcode and operand requirements.
3. EXECUTE:
◦ The CU sends control signals to perform the action (e.g., ALU performs calculations, data loaded into ACC, or
data written to RAM).
IGCSE Computer Science (2210/0478) - Chapter 3: Hardware Page 2 of 6
0478)
CHAPTER 3: HARDWARE — COMPREHENSIVE STUDY & REVISION GUIDE
Syllabus Reference: Section 3.1 - 3.4 Target Grades: A* / Grade 9 Specialist Notes
Topic: Computer Architecture, Input/Output, Storage & Network Format: High-Yield Revision Summary for Stuvia
Hardware Sales
This study guide covers the entire Chapter 3 specification for Cambridge IGCSE Computer Science ().
Designed to meet exam mark schemes, it features Von Neumann architecture, Fetch-Decode-Execute cycles, sensors,
primary/secondary/target storage technologies, and network devices.
1. COMPUTER ARCHITECTURE & THE CPU
1.1 Von Neumann Architecture
The Von Neumann architecture is the theoretical design for modern general-purpose electronic computers. Its defining
characteristic is that data and program instructions are stored together in the same shared memory (RAM).
DIAGRAM 3.1: VON NEUMANN CPU ARCHITECTURE & BUS CONNECTIONS
+-----------------------------------------------------------------------+
| CENTRAL PROCESSING UNIT |
| |
| +-----------------------+ +-----------------------+ |
| | CONTROL UNIT (CU) | | ALU (Arithmetic | |
| | | | Logic Unit) | |
| | • Coordinates CPU | | • Arithmetic (+,-) | |
| | • Contains PC & CIR | | • Logical (AND, OR) | |
| +-----------+-----------+ +-----------+-----------+ |
| | | |
| +-------------------+-------------------+ |
| | |
| +-------------------------------+-------------------------------+ |
| | INTERNAL REGISTERS | |
| | • PC (Program Counter) • MAR (Memory Address Reg) | |
| | • CIR (Current Instruction Reg) • MDR (Memory Data Reg) | |
| | • ACC (Accumulator) | |
| +-------------------------------+-------------------------------+ |
+-----------------------------------|-----------------------------------+
|
========================+========================
|| CONTROL BUS (Unidirectional/Bidirect) ||
|| ADDRESS BUS (Unidirectional) ||
|| DATA BUS (Bidirectional) ||
========================+========================
|
+-----------------------------------|-----------------------------------+
| MAIN MEMORY (RAM) |
| |
| [ Address 0x00 ] -> Instruction / Data |
| [ Address 0x01 ] -> Instruction / Data |
+-----------------------------------------------------------------------+
IGCSE Computer Science (2210/0478) - Chapter 3: Hardware Page 1 of 6
, 1.2 CPU Components & Registers
Component / Register Abbr. Detailed Function & Exam Description
Controls signals, synchronizes CPU operations using system clock pulses, and
Control Unit CU
decodes instructions.
Performs mathematical operations (addition, subtraction) and logical comparisons
Arithmetic Logic Unit ALU
(AND, OR, NOT, >, <).
Holds the memory address of the next instruction to be fetched from RAM.
Program Counter PC
Increments automatically.
Memory Address Holds the memory address currently being read from or written to in RAM. Connected
MAR
Register directly to the Address Bus.
Holds the actual data or instruction fetched from memory or awaiting write back.
Memory Data Register MDR
Connected directly to the Data Bus.
Current Instruction
CIR Holds the instruction currently being decoded and executed by the CU.
Register
Temporary register that stores the immediate mathematical or logical results produced
Accumulator ACC
by the ALU.
1.3 System Buses
Bus Name Directionality Function & Purpose
Address Unidirectional (CPU → Carries memory addresses from the MAR to RAM/I-O units. Width determines
Bus Memory) addressable memory capacity.
Bidirectional (CPU ↔ Carries actual data and instructions between CPU registers (MDR) and
Data Bus
Memory) Memory/Peripherals.
Control Bidirectional / Carries control and timing signals (e.g., Read, Write, Interrupt, Clock) across
Bus Unidirectional components.
1.4 The Fetch-Decode-Execute (F-D-E) Cycle
Step-by-Step F-D-E Sequence (Must memorize for 4–6 mark questions):
1. FETCH:
◦ The address of the next instruction in the PC is copied to the MAR.
◦ The PC is incremented by 1 to point to the next instruction.
◦ The instruction stored at the address in MAR is fetched via the Data Bus into the MDR.
◦ The instruction is transferred from the MDR into the CIR.
2. DECODE:
◦ The Control Unit (CU) decodes the instruction in the CIR to determine opcode and operand requirements.
3. EXECUTE:
◦ The CU sends control signals to perform the action (e.g., ALU performs calculations, data loaded into ACC, or
data written to RAM).
IGCSE Computer Science (2210/0478) - Chapter 3: Hardware Page 2 of 6
