Electronic Devices and Nanotechnology
Topic 1-1:
Introduction to Nano-Device Fabrication
,Integrated Circuit Device Density
Historical Progression
Technology node Rate: -15.5%/yr
(e.g. ‘10 µm node’) Halving every 4.5 years.
Michel Calame, Basel
Commercial Development
2020: TSMC and Samsung deliver 5 nm chips
Future
3 nm - ~ 2022
2 nm - ~ >2023 ??
, Moore’s “Law”
1965:
“The complexity for minimum component
costs has increased at a rate of roughly a
factor of two per year.”
G.E. Moore, Elec. Mag., April 1965
The number of transistors on a chip doubles every 2 years
The minimum feature size x every 2 years
The cost of a manufacturing plant doubles every 2 years
Prof. D.J. Paul, University of Glasgow
Topic 1-1:
Introduction to Nano-Device Fabrication
,Integrated Circuit Device Density
Historical Progression
Technology node Rate: -15.5%/yr
(e.g. ‘10 µm node’) Halving every 4.5 years.
Michel Calame, Basel
Commercial Development
2020: TSMC and Samsung deliver 5 nm chips
Future
3 nm - ~ 2022
2 nm - ~ >2023 ??
, Moore’s “Law”
1965:
“The complexity for minimum component
costs has increased at a rate of roughly a
factor of two per year.”
G.E. Moore, Elec. Mag., April 1965
The number of transistors on a chip doubles every 2 years
The minimum feature size x every 2 years
The cost of a manufacturing plant doubles every 2 years
Prof. D.J. Paul, University of Glasgow
