WGU C952 Computer Architecture Terms you should know Correct Explained

WGU C952 Computer Architecture Terms you should know Correct Explained WGU C952 Computer Architecture Terms you should know Correct Explained Register File << correct answer >> A state element that consists of a set of registers that can be read and written by supplying a register number to be accessed. provides 1024 scalar 32-bit registers for up to 64 threads. machine language << correct answer >> The language made up of binary-coded instructions that is used directly by the computer system software << correct answer >> The set of programs that enables a computer's hardware devices and application software to work together; it includes the operating system and utility programs. operating system << correct answer >> (computer science) software that controls the execution of computer programs and may provide various services Assembly Language << correct answer >> Programming language that has the same structure and set of commands as machine languages but allows programmers to use symbolic representations of numeric machine code. IBM 360/91 << correct answer >> Introduced many new concepts, including dynamic detection of memory hazards, generalized forwarding, and reservation stations. Tomasulo's algorithm The internal organization of the 360/91 shares many features with the Pentium III and Pentium 4, as well as with several other microprocessors. One major difference was that there was no branch prediction in the 360/91 and hence no speculation. Another major difference was that there was no commit unit, so once the instructions finished execution, they updated the registers. Dynamic Random Access Memory (DRAM) << correct answer >> Memory built as an integrated circuit; it provides random access to any location. Access times are 50 nanoseconds and cost per gigabyte in 2012 was $5 to $10. Multiple DRAMs are used together to contain the instructions and data of a program. In contrast to sequential access memories, such as magnetic tapes, the RAM portion of the term DRAM means that memory accesses take basically the same amount of time no matter what portion of the memory is read. Modern DRAMS consist of rows in each bank frame buffering << correct answer >> A portion of RAM containing a bitmap that drives a video display. It is a memory buffer containing a complete frame of data. The image to be represented onscreen is stored in the frame buffer, and the bit pattern per pixel is read out to the graphics display at the refresh rate. The animation below shows a frame buffer with a simplified design of just 4 bits per pixel. Datapath << correct answer >> The component of the processor that performs arithmetic operations Control << correct answer >> The component of the processor that commands the datapath, memory, and I/O devices according to the instructions of the program. Integrated circuit << correct answer >> Also called a chip. A device combining dozens to millions of transistors. Central processor unit (CPU) << correct answer >> Also called processor. The active part of the computer, which contains the datapath and control and which adds numbers, tests numbers, signals I/O devices to activate, and so on. Static random access memory (SRAM) << correct answer >> Also memory built as an integrated circuit, but faster and less dense than DRAM. Instruction set architecture << correct answer >> Also called architecture. An abstract interface between the hardware and the lowest-level software that encompasses all the information necessary to write a machine language program that will run correctly, including instructions, registers, memory access, I/O, and so on. Application binary interface (ABI) << correct answer >> The user portion of the instruction set plus the operating system interfaces used by application programmers. It defines a standard for binary portability across computers. Volatile memory << correct answer >> Storage, such as DRAM, that retains data only if it is receiving power. Nonvolatile Memory << correct answer >> A form of memory that retains data even in the absence of a power source and that is used to store programs between runs. A DVD disk is nonvolatile. Magnetic disk << correct answer >> Also called hard disk. A form of nonvolatile secondary memory composed of rotating platters coated with a magnetic recording material. Because they are rotating mechanical devices, access times are about 5 to 20 milliseconds and cost per gigabyte in 2012 was $0.05 to $0.10 Main memory << correct answer >> Also called primary memory. Memory used to hold programs while they are running; typically consists of DRAM in today's computers. Secondary memory << correct answer >> Nonvolatile memory used to store programs and data between runs; typically consists of flash memory in PMDs and magnetic disks in servers. Flash memory << correct answer >> A nonvolatile semiconductor memory. It is cheaper and slower than DRAM but more expensive per bit and faster than magnetic disks. Access times are about 5 to 50 microseconds and cost per gigabyte in 2012 was $0.75 to $1.00. Single Instruction Single Data (SISD) << correct answer >> A uniprocessor Multiple Instruction Multiple Data (MIMD) << correct answer >> A multiprocessor. Single Program, Multiple Data Streams (SPMD) << correct answer >> The conventional MIMD programming model, where a single program runs across all processors. Single Instruction Stream, Multiple Data Streams (SIMD) << correct answer >> The same instruction is applied to many data streams, as in a vector processor. Data-level parallelism << correct answer >> Parallelism achieved by performing the same operation on independent data vector-based code << correct answer >> conventional code << correct answer >> LEGv8 << correct answer >> assembly instructions multimedia extensions (MMX) << correct answer >> An expanded set of instructions supported by a processor that provides multimedia-specific functions. data hazard (pipeline data hazard) << correct answer >> When a planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction are not yet available. forwarding (bypassing) << correct answer >> A method of resolving a data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer-visible registers or memory Structural hazard << correct answer >> When a planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute. Pipelining << correct answer >> Technique that allows the CPU to work on more than one instruction at a time Formula total process time = [longest task * (total load -1)] + total load time R-format ALU operations << correct answer >> Requires register file and the ALU. Program Counter (PC) << correct answer >> The register that contains the address of the next instruction to be executed output << correct answer >> The results of the operation of any system. temporal locality << correct answer >> The principle stating that if a data location is referenced then it will tend to be referenced again soon. spatial locality << correct answer >> The principle stating that if a data location is referenced, data locations with nearby addresses will tend to be referenced soon. Memory hierarchy << correct answer >> A structure that uses multiple levels of memories; as the distance from the processor increases, the size of the memories and the access time both increase. Block (or line) << correct answer >> The minimum unit of information that can be either present or not present in a cache. Hit rate << correct answer >> The fraction of memory accesses found in a level of the memory hierarchy. Miss rate << correct answer >> The fraction of memory accesses not found in a level of the memory hierarchy miss penalty << correct answer >> The time required to fetch a block into a level of the memory hierarchy from the lower level, including the time to access the block, transmit it from one level to the other, insert it in the level that experienced the miss, and then pass the block to the requestor. Hit time << correct answer >> The time required to access a level of the memory hierarchy, including the time needed to determine whether the access is a hit or a miss. Parallelization << correct answer >> consist of dividing a program into separate components that run in parallel on individual computers in the cluster superscalar << correct answer >> Technique primarily associated with hardware. Functional units (ALU, Floating Point Unit, Load/Store Unit) are duplicated in the pipeline of a superscalar processor which allows the hardware to issue multiple instructions to each unit simultaneously. ARM architecture << correct answer >> can support 16-bit Amdahl's Law << correct answer >> A formula used to find the maximum improvement possible by improving a particular part of a system. In parallel computing, Amdahl's law is mainly used to predict the theoretical maximum speedup for program processing using multiple processors multiprocessor << correct answer >> A term used to refer to a computer with more than one CPU. Uniform Memory Access (UMA) << correct answer >> A multiprocessor in which latency to any word in main memory is about the same no matter which processor requests the access. Non-Uniform Memory Access (NUMA) << correct answer >> Varying system memory access times, because of system hardware. loop unrolling << correct answer >> A technique to get more performance from loops that access arrays, in which multiple copies of the loop body are made and instructions from different iterations are scheduled together. Blocking << correct answer >> a failure to retrieve information that is available in memory even though you are trying to produce it can help reduce cache miss rate Set Associative Cache << correct answer >> A cache that has a fixed number of locations (at least two) where each block can be placed. RAID 0 (Disk Striping) << correct answer >> Disk Striping. Disk striping requires at least two drives. It does not provide redundancy to data. If any one drive fails, all data is lost. RAID 1 (mirroring) << correct answer >> Two drives are used in unison, and all data is written to both drives, giving you a mirror or extra copy of the data, in the case that one drive fails RAID 2 << correct answer >> Bit-level striping with dedicated Hamming-code parity. OBSOLETE. RAID 3 << correct answer >> Byte-level striping with dedicated parity. OBSOLETE, replaced with RAID 5. RAID 4 << correct answer >> Block-level striping with dedicated parity. Not often used, replaced with RAID 5. RAID 5 << correct answer >> Disk striping with parity. RAID-5 uses three or more disks and provides fault tolerance. RAID 6 << correct answer >> Disk striping with parity. RAID-6 uses four or more disks and provides fault tolerance. It can survive the failure of two drives. silicon crystal ingot << correct answer >> A rod composed of a silicon crystal that is between 8 and 12 inches in diameter and about 12 to 24 inches long. wafer << correct answer >> A slice from a silicon ingot no more than 0.1 inches thick, used to create chips. Instruction Set Architecture (ISA) << correct answer >> Also called architecture. An abstract interface between the hardware and the lowest-level software that encompasses all the information necessary to write a machine language program that will run correctly, including instructions, registers, memory access, I/O, and so on Application Binary Interface (ABI) << correct answer >> The user portion of the instruction set plus the operating system interfaces used by application programmers. It defines a standard for binary portability across computers. Transistor << correct answer >> An on/off switch controlled by an electric signal very large-scale integrated (VLSI) circuit << correct answer >> A device containing hundreds of thousands to millions of transistors. silicon << correct answer >> A natural element that is a semiconductor 1. Excellent conductors of electricity (using either microscopic copper or aluminum wire) 2. Excellent insulators from electricity (like plastic sheathing or glass) 3. Areas that can conduct or insulate under special conditions (as a switch) Semiconductor << correct answer >> A substance that can conduct electricity under some conditions Die << correct answer >> The individual rectangular sections that are cut from a wafer, more informally known as chips. complementary metal-oxide semiconductor (CMOS) << correct answer >> Dominant technology for integrated circuits LEGv8 << correct answer >> Assembly Language LEGv8 word << correct answer >> A natural unit of access in a computer, usually a group of 32 bits LEGv8 doubleword << correct answer >> Another natural unit of access in a computer, usually a group of 64 bits (8 bytes); corresponds to the size of a register in the LEGv8 architecture LEGv8 register << correct answer >> 64 bits wide more registers will lead to a slower clock frequency Smaller is faster << correct answer >> A very large number of registers may increase the clock cycle time simply because it takes electronic signals longer when they must travel farther. Guidelines such as "smaller is faster" are not absolutes; 31 registers may not be faster than 32. Even so, the truth behind such observations causes computer designers to take them seriously. In this case, the designer must balance the craving of programs for more registers with the designer's desire to keep the clock cycle fast. Another reason for not using more than 32 is the number of bits it would take in the instruction format. Data transfer instruction << correct answer >> A command that moves data between memory and registers. Address << correct answer >> A value used to delineate the location of a specific data element within a memory array. load << correct answer >> data transfer instruction that copies data from memory to a register LEGv8 LDUR << correct answer >> The sum of the constant portion of the instruction and the contents of the second register forms the memory address The U in LDUR stands for unscaled immeditate base address << correct answer >> starting address of an array in memory (5000 below) base register << correct answer >> register that holds an array's base address (X22 below) offset << correct answer >> a constant value added to a base address to locate a particular array element (8 below) Big Endian << correct answer >> A CPU or memory architecture in which the most significant byte is stored at the lowest memory address. store register << correct answer >> instruction complementary to load. It copies data from register to memory. the format is similar to load; name of the operation, followed by the register to be stored, then the base register, and finally the offset to select the array element. LEGv8 STUR << correct answer >> store register spilling register << correct answer >> The process of putting less frequency used variables (or those needed later into memory) reservation station << correct answer >> A buffer within a functional unit that holds the operands and the operation. commit unit << correct answer >> The unit in a dynamic or out-of-order execution pipeline that decides when it is safe to release the result of an operation to programmer-visible registers and memory. Reorder Buffer << correct answer >> The buffer that holds results in a dynamically scheduled processor until it is safe to store the results to memory or a register. out-of-order execution << correct answer >> A situation in pipelined execution when an instruction blocked from executing does not cause the following instructions to wait. in-order commit << correct answer >> A commit in which the results of pipelined execution are written to the programmer-visible state in the same order that instructions are fetched. VLIW << correct answer >> A style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields ARMv8 virtual memory << correct answer >> 64-bit addressed. The upper 16 bits are not used, so only 48 bits are used. it is allocated by loads the page table register to refer to the page table of the process. ARMv8 allows implementations with a smaller virtual address. It also allows physical addresses as large as 48 bits. It supports three options for a minimum page or granule size: 4, 16, and 64 Kibibyte. address translation (address mapping) << correct answer >> the process by which a virtual address is mapped to an address used to access memory Exception Syndrome Register (ESR) << correct answer >> record the cause of the exception FADDS, FSUBS << correct answer >> Single-precision arithmetic FADDD, FSUBD, FMULD, FDIVD << correct answer >> Double-precision arithmetic FCMPS, FCMPD << correct answer >> Single- and double-precision comparison motivations for virtual memory << correct answer >> 1. To allow efficient and safe sharing of memory among several programs and to remove the programming burdens of a small, limited amount of main memory [still being used today] 2. To allow a single user program to exceed the size of primary emmory. virtual memory << correct answer >> A technique that uses main memory as a "cache" for secondary storage The address is broken into a virtual page number and a page offset physical address << correct answer >> An address in main memory. Protection << correct answer >> A set of mechanisms for ensuring that multiple processes sharing the processor, memory or I/O devices cannot interfere, intentionally or unintentionally, with one another by reading or writing each other's data. These mechanism also isolate the operating system from a user process. page << correct answer >> a virtual memory block. all virtual memory system relocate the program as a set of fixed-size blocks page fault << correct answer >> a virtual memory miss virtual address << correct answer >> An address that corresponds to a location in virtual space and is translated by address mapping to a physical address when memory is accessed. page table << correct answer >> The table containing the virtual to physical address translations in a virtual memory system. The table, which is stored in memory, is typically indexed by the virtual page number; each entry in the table contains the physical page number for that virtual page if the page is currently in memory. indexed by the page number from the virtual address swap space << correct answer >> The space on the disk reserved for the full virtual memory space of a process Reference Bit (Use Bit or Access Bit) << correct answer >> A field that is set whenever a page is accessed and that is used to implement LRU or other replacement schemes. ARMv8 calls it an access bit Techniques for reducing total max storage required << correct answer >> 1. Keep a limit register that restrict the size of the page table for a given process and add more entries as needed. 2. A limit register for each segment specifies the current size of the segment, which grows in units of pages. This type of segmentation is used by many architectures, including ARMv8 and MIPS. Unlike the type of segmentation discussed in a previous elaboration, this form of segmentation is invisible to the application program, although not to the operating system. This does not work when the address space is used sparsely rather than contiguous. 3. Apply a hashing function to the virtual address so that the table need to be only the size of the number of physical pages in the main memory. AKA inverted page table. Lookup process can be more complex because it is not indexed 4. Allow the page tables to be paged. It works by allowing the page tables to reside in the virtual address space. 5. Multiple levels of page tables and is the solution that ARMv8 uses to reduce the memory footprint of address translation. This scheme allows the address space to be used in a sparse fashion (multiple noncontiguous segments can be active) without having to allocate the entire page table. Useful with very large address spaces and in software systems that require noncontiguous allocation. The primary disadvantage of this multi-level mapping is the more complex process for address translation. Least Recently Used (LRU) << correct answer >> A replacement scheme in which the block replaced is the one that has been unused for the longest time. dirty bit << correct answer >> indicates if a page has been written since being read into memory Translation Lookaside Buffer (TLB) << correct answer >> A cache that keeps track of recently used address mappings to try to avoid an access to the page table. Can be used to improve access performance by relying on locality of reference TLB size: 16-512 entries Block size: 1-2 page table entries (typically 4-8 bytes each) Hit time: 0.5-1 clock cycle Miss penalty: 10-100 clock cycles Miss rate: 0.01%-1% Exception Enable (Interrupt Enable) << correct answer >> A signal or action that controls whether the process responds to an exception or not; necessary for preventing the occurrence of exceptions during intervals before the processor has safely saved the state needed for restart. The Intrinsity FastMATH TLB << correct answer >> The memory system uses 4 KiB pages and just a 32-bit address space; thus, the virtual page number is 20 bits long. The physical address is the same size as the virtual address. The TLB contains 16 entries, it is fully associative, and it is shared between the instruction and data references. Each entry is 64 bits wide and contains a 20-bit tag (which is the virtual page number for that TLB entry), the corresponding physical page number (also 20 bits), a valid bit, a dirty bit, and other bookkeeping bits. Like most ARMv8 systems, it uses software to handle TLB misses. TLB miss << correct answer >> indicates that a page is not in the TLB. Another process then finds and loads the missing page. TLB events combination << correct answer >> +-------+-------------+-------+------------+ | TLB | Page table | Cache | Result | +-------+-------------+-------+------------+ | Hit | Hit | Miss | Possible | | Miss | Hit | Hit | Possible | | Miss | Hit | Miss | Possible | | Miss | Miss | Miss | Possible | | Hit | Miss | Miss | Impossible | | Hit | Miss | Hit | Impossible | | Miss | Miss | Hit | Impossible | +-------+-------------+-------+------------+ virtually addressed cache << correct answer >> A cache that is accessed with a virtual address rather than a physical address Does not use the TLB Aliasing << correct answer >> A situation in which two addresses access the same object; it can occur in the virtual memory when there are two virtual addresses for the same physical page Physically addressed cache << correct answer >> A cache that is addressed by a physical address. context switch << correct answer >> A changing of the internal state of the processor to allow a different process to use the processor that includes saving the state needed to return to the currently executing process. syscall << correct answer >> Generates a system call exception that transfers control to the processor and allows access to a dedicated location in supervisor code space. The process returns to user mode via the RET instruction. L1 cache (primary cache) << correct answer >> a cache for a cache L2 cache << correct answer >> A cache for main memory It is faster than memory, but tends to be larger and slower than the L1 cache Virtual machines << correct answer >> Developed in the mid-1960s. Benefits: Managing software Managing hardware virtual machine manager (VMM) << correct answer >> Hypervisor usually, run in system mode while guest VM run in user mode. hardware = host VMs = guest It determines how to map virtual resources to physical resources. It is also much smaller than a traditional OS; the isolation portion of a VMM is only 10,000 lines of code Instruction Set Architecture (ISA) << correct answer >> The part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. Memory Hierarchy << correct answer >> concept that is necessary for the CPU to be able to manipulate data. Strong scaling << correct answer >> Speed-up achieved on a multiprocessor without increasing the size of the problem. Weak scaling << correct answer >> Speed-up achieved on a multiprocessor while increasing the size of the problem proportionally to the increase in the number of processors. Not bound by Amdah's Law multiprocessor architecture << correct answer >> A unified graphics and computing multiprocessor executes vertex, geometry, and pixel fragment shader programs, and parallel computing programs advantages: Increased throughput Cost saving Increased reliability Streaming processor (SP) << correct answer >> the primary thread instruction processor in the multiprocessor Special function unit (SFU) << correct answer >> Compute 32-bit floating-point approximations to reciprocal, reciprocal square root, and key transcendental functions. It also implements 32-bit floating-point planar attribute interpolation for pixel shaders, providing accurate interpolation of attributes such as color, depth, and texture coordinates. Uniform Memory Access (UMA) << correct answer >> A multiprocessor in which latency to any word in main memory is about the same no matter which processor requests the access. Non-Uniform Memory Access (NUMA) << correct answer >> Varying system memory access times, because of system hardware. throughput << correct answer >> the amount of work performed by a system during a given period of time CPU Time Formula << correct answer >> (Instructions) x (CPI) x (Clock Cycle Time) Set Associative Cache << correct answer >> A cache that has a fixed number of locations (at least two) where each block can be placed (Block number) modulo (Num set in the cache) Variable one-way - Original set two-way - Will improve overall performance four-way eight-way Fully associative cache << correct answer >> A cache structure in which a block can be placed in any location in the cache. CDC 6600 << correct answer >> This system is widely considered to have been the first supercomputer. Also first load-store architecture Tomasulo's Algorithm << correct answer >> An algorithm for dynamic scheduling and out-of-order execution uses dynamic hazard detection, generalized forwarding, and reservation stations. IBM 7030 << correct answer >> AKA Stretch Produced with the goal of being 100 times faster than the previous IBM 704 Imprecise interupt << correct answer >> The unpopularity of imprecise interrupts led to the standard of commit units in dynamically scheduled pipelined processors Digital Equipment Corporation (DEC) << correct answer >> A major American company in the computer industry from the 1950s to the 1990s PDP-8 << correct answer >> First commercial minicomputer introduced by Digital Equipment Corporation cost under $20,000 Intel 4004 << correct answer >> First microprocessor supercomputer << correct answer >> a particularly powerful mainframe computer. Seymour Cray << correct answer >> American inventor of the Cray supercomputer. Least Significant Bits << correct answer >> The two bits furthest to the right most significant bit << correct answer >> left most bit Sign and magnitude representation << correct answer >> a signed number representation where a single bit is used to represent the sign and the remaining bits represent the magnitude sign extension << correct answer >> function of a copy signed load is to copy the sign repeatedly to fill the rest of the register LEGv8 fields << correct answer >> 1. opcode - 11 bits - basic operation of the instruction 2. rm - 5 bits - the second register source operand 3. shamt - 6 bits - shift amount 4. rn - 5 bits - the first register source operand 5. rd - 5 bits - the register destination operand B.EQ << correct answer >> equal B.NE << correct answer >> not equal B.LT << correct answer >> less than B.LE << correct answer >> less than or equal to B.GT << correct answer >> greater than B.GE << correct answer >> greater than or equal to condition codes (flag) << correct answer >> 4 bits are used In MIPS, two registers are compared and the result of the comparison is stored in a third register. Then a conditional branching statement assess the value of the third register to see if the condition is true or false. Negative (N) Zero (Z) Overflow (V) Carry (C) B.MI << correct answer >> branch on minus N=1 B.PL << correct answer >> branch on plus N=0 B.VS << correct answer >> branch on overflow set V=1 B.VC << correct answer >> branch on overflow clear V=0 branch-and-link instruction << correct answer >> An instruction that branches to an address simultaneously saves the address of the following instruction in a register (LR or X30 in LEGv8). Return address << correct answer >> A link to the calling site that allows a procedure to return to the proper address; in MIPS it is stored in register LR (X30) Caller << correct answer >> The program that instigates a procedure and provides the necessary parameter values. Callee << correct answer >> A procedure that executes a series of stored instructions based on parameters provided by the caller and then returns control to the caller. Program counter (PC) << correct answer >> The register that contains the address of the next instruction to be executed overflow (floating point) << correct answer >> A situation in which a positive exponent becomes too large to fit in the exponent field. underflow (floating point) << correct answer >> A situation in which a negative exponent becomes too large to fit in the exponent field. double precision << correct answer >> A floating-point value represented in 64-bit words. single precision << correct answer >> A floating-point value represented in a single 32-bit word. subword parallelism (data level parallelism) << correct answer >> Given that the parallelism occurs within a wide word They are known as well as vector or SIMD, for single instruction, multiple data (see COD Section 6.6 (Introduction to graphics processing units)). The rising popularity of multimedia applications led to arithmetic instructions that support narrower operations that can easily compute in parallel. accumulator << correct answer >> Archaic term for register. On-line use of it as a synonym for "register" is a fairly reliable indication that the user has been around quite a while Load-Store Architecture (register-register architecture) << correct answer >> An instruction set architecture in which all operations are between registers and data memory may only be accessed via loads of stores RISC Architecture << correct answer >> Reduced instruction set computer architecture Relies on small and simple instructions instead of more complex and specialized instructions. Most current instruction set employ the architecture model High-level-language computer architecture << correct answer >> Proposed in the 1960s, high-level-language architecture failed to make much of a commercial impact. Better compilers and programming languages, and growing memory sizes led to this architecture's demise. Accumulator Architecture << correct answer >> One operand of a binary operation is implicitly in the accumulator The earliest computers had only one register to perform arithmetic operations. All operations would accumulate in the single register, called the accumulator. Stack Architecture << correct answer >> no register In the 1960s, believing that compilers were not good at register allocation, some companies eliminated registers and instead transferred operands onto and off of the stack, similar to what was done in Hewlett-Packard calculators. ARMv7 << correct answer >> ARM started as the processor for the Acorn computer, hence its original name of Acorn RISC Machine. The Berkeley RISC papers influenced its architecture. ARMv8 << correct answer >> extension of ARMv7 with 64-bit address. ARM took the opportunity to redesign the instruction set to make it look much more like MIPS than like earlier ARM versions SDIV << correct answer >> Signed divide SUBI << correct answer >> subtract immediate MVZ << correct answer >> move wide with zero LDUR << correct answer >> load register STUR << correct answer >> store register LSL << correct answer >> logical shift left LSR << correct answer >> Logical Shift Right Coprocessor << correct answer >> an additional chip that accelerates a portion of the work of a processor; in this case, it accelerated floating-point computation Combinational element << correct answer >> An operational element, such as an AND gate or an ALU. State element << correct answer >> A memory element, such as a register or a memory. clocking methodology << correct answer >> defines when signals can be read and when they can be written Edge-triggered clocking << correct answer >> any values stored in a sequential logic element are updated only on a clock edge Edge-triggered state elements make simultaneous reading and writing both possible and unambiguous. Control signal << correct answer >> A signal used for multiplexor selection or for directing the operation of a functional unit; contrasts with a data signal, which contains information that is operated on by a functional unit. Asserted << correct answer >> The signal is logically high or true Deasserted << correct answer >> The signal is logicall low or false. rising clock edge << correct answer >> 0 to 1 falling clock edge << correct answer >> 1 to 0 Sign-extend << correct answer >> To increate the size of data item by replicating the high-order sign bit of the original data item in the high-order bits of the larger, destination data item. Branch target address << correct answer >> the address specified in a branch, which becomes the new program counter if the branch is taken. In the LEGv8 archtecture, the branch target is given by the sum of the offset field of the instruction and the address of the branch Branch taken << correct answer >> A branch where the branch condition is satisfied and the program counter becomes the branch target. All unconditional branches are taken branches branch not taken or (untaken branch) << correct answer >> A branch where the branch condition is false and the program counter (PC) becomes the address of the instruction that sequentially follows the branch. ALUOp << correct answer >> the 4-bit ALU control input using a small control unit that has as inputs the opcode field of the instruction and a 2-bit control field indicates whether the operation to be performed should be add (00) for loads and stores, pass input b (01) for CBZ, or be determined by the operation encoded in the opcode field (10) 10 is ORR, AND, SUB, ADD (R-type) 00 is LDUR, STUR 01 is CBZ ALU control lines << correct answer >> 0000 is AND 0001 is OR 0010 is ADD 0110 is SUBTRACT 0111 PASS INPUT B 1100 is NOR Pipeline stall (bubble) << correct answer >> a stall initiated in order to resolve a hazard Load-use data hazard: << correct answer >> A specific form of data hazard in which the data being loaded by a load instruction has not yet become available when it is needed by another instruction. control hazard (branch hazard) << correct answer >> When the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed; that is, the flow of instruction addresses is not what the pipeline expected. Branch prediction << correct answer >> A method of resolving a branch hazard that assumes a given outcome for the branch and proceeds from that assumption rather than waiting to ascertain the actual outcome. five-stage pipeline << correct answer >> five instructions will be in execution during any single clock cycle 1. IF - instruction fetch 2. ID - instruction decode and register file read 3. EX - execution or address calculation 4. MEM - data memory access 5. WB - write back Instruction Fetch (IF) << correct answer >> Move instruction from memory to the control unit Instruction decode (ID) << correct answer >> Pull apart the instruction, set up the operation in the ALU, and compute the source and destination operand addresses Execute (EX) << correct answer >> ALU is used to perform the instruction's operation or to compute an address, or an adder is used for branches; both are depicted using an ALU symbol. Data memory access (MEM) << correct answer >> the data memory (DM) may be read (for a load instruction) or written (for a store instruction). For load, the right half is shaded, indicating read. (For store, the left half would be shaded). Write back (WB) << correct answer >> the register file (Reg) may be written by certain instructions (like R-type instructions). The left half is shaded to indicate write (vs. read). Although two Reg icons appear in the stylized depictions, only one register file exists. Branch prediction buffer << correct answer >> Also called branch history table. A small memory that is indexed by the lower portion of the address of the branch instruction and that contains one or more bits indicating whether the branch was recently taken or not. Dynamic branch prediction << correct answer >> prediction of branches at runtime using runtime information Branch target buffer << correct answer >> A structure that caches the destination PC or destination instruction for a branch. It is usually organized as a cache with tags, making it more costly than a simple prediction buffer. Correlating predictor << correct answer >> A branch predictor that combines local behavior of a particular branch and global information about the behavior of some recent number of executed branches. Tournament branch predictor << correct answer >> A branch predictor with multiple predictions for each branch and a selection mechanism that chooses which predictor to enable for a given branch. Microarchitecture << correct answer >> The organization of the processor, including the major functional units, their interconnection, and control. Architectural registers << correct answer >> The instruction set of visible registers of a processor; for example, in MIPS, these are the 32 integer and 16 floating point registers Three Cs model << correct answer >> A cache model in which all cache misses are classified into one of three categories: compulsory misses, capacity misses, and conflict misses. compulsory miss (cold-start miss) << correct answer >> a cache miss caused by the first access to a block that has never been in the cache Both large block sizes and prefetching may reduce compulsory misses capacity miss << correct answer >> A cache miss that occurs because the cache, even with full associativity, cannot contain all the blocks needed to satisfy the request. Increase cache size may decrease capacity misses and increase access time conflict miss (collision miss) << correct answer >> A cache miss that occurs in a set-associative or direct-mapped cache when multiple blocks compete for the same set and that are eliminated in a fully associative cache of the same size Increases associativity may decrease miss rate and increase access time. Finite-state machine << correct answer >> A sequential logic function consisting of a set of inputs and outputs, a next-state function that maps the current state and the inputs to a new state, and an output function that maps the current state and possibly the inputs to a set of asserted outputs. Next-state machine << correct answer >> A combinational function that, given the inputs and the current state, determines the next state of a finite-state machine. cache ready signal << correct answer >> set in the Compare Tag state if requested read or write is a hit memory ready signal << correct answer >> set in the Write Back state when a block is written to memory and in the Allocate state when a memory read is completed. Consistency << correct answer >> ensure that writes to a location by different processors are seen in the same order by all processors. It is defines when written values will be returned by a read Coherence << correct answer >> ensures that a read of a data item returns the most recently written value of that data item. It defines what values can be returned by a read Write serialization << correct answer >> Method that ensures writes to a location are seen in the same order by all processors. Maintaining the order of writes to a given location ensures that all processors sharing memory read the correct data. snooping << correct answer >> a popular cache coherence protocol. Each cache contains a copy of data from a block of physical memory along with a copy of the sharing status of that block. Each cache contains a controller that monitors, or snoops, activity on a shared communication medium to determine if any action is needed to ensure cache coherence. write invalidate protocol << correct answer >> enforcing coherence is to ensure that a processor has exclusive access to a data item before it writes that item R-Format Instructions << correct answer >> They all read two registers, perform an ALU operation on the contents of the registers, and write the result to a register. We call these instructions either R-type instructions or arithmetic-logical instructions (since they perform arithmetic or logical operations). This instruction class includes ADD, SUB, AND, and ORR, Need an ALU to operate on the values read from the registers. Multiprocessing << correct answer >> The simultaneous execution of two or more instructions at the same time. Multithreading << correct answer >> allows multiple commands, or threads to run simultaneously