Making virtual Chips
● File extension is .hdl
● “CHIP <nameOfFile>” at the start
● Use curly braces and ; to end lines
● Case sensitive
● Two section are separated by “PARTS:”
○ Top part is inputs, outputs
○ Bottom is how its all connected
● IN for input, OUT for output
● Make gates by specifying the name of the gate (case sensitive, need a capital letter), then use brackets to specify how its connected
○ And(a=x, b=y, out=A2n)
○ Means a is connected to x, b to y, and outputs to ‘wire’ A2n
○ Not(in=A2n, out=out)
○ Input is the output of the And gate, outputting to the chip
○ Because the name of the ‘wire’ is the same, they get connected
● [] are used to identify a bus (multiple bits)
,
● File extension is .hdl
● “CHIP <nameOfFile>” at the start
● Use curly braces and ; to end lines
● Case sensitive
● Two section are separated by “PARTS:”
○ Top part is inputs, outputs
○ Bottom is how its all connected
● IN for input, OUT for output
● Make gates by specifying the name of the gate (case sensitive, need a capital letter), then use brackets to specify how its connected
○ And(a=x, b=y, out=A2n)
○ Means a is connected to x, b to y, and outputs to ‘wire’ A2n
○ Not(in=A2n, out=out)
○ Input is the output of the And gate, outputting to the chip
○ Because the name of the ‘wire’ is the same, they get connected
● [] are used to identify a bus (multiple bits)
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