Computer Architecture - CEA201 - FPT Exam All | CEA201 – Full Exam Bank_ Questions & Answers Fall .

CEA201 – Full Exam Bank_ Questions & Answers Fall . There is a tremendous variety of products, from single-chip microcomputers costing a few dollars to supercomputers costing tens of millions of dollars that can rightly claim the name "computer". A. True B. False The variety of computer products is exhibited only in cost. A. True B. False Computer organization refers to attributes of a system visible to the programmer. A. True B. False Changes in computer technology are finally slowing down. A. True B. False The textbook for this course is about the structure and function of computers. A. True B. False The number of bits used to represent various data types is an example of an architectural attribute. A. True B. False Interfaces between the computer and peripherals is an example of an organizational attribute. A. True B. False Historically the distinction between architecture and organization has not been an important one. A. True B. False A particular architecture may span many years and encompass a number of different computer models, its organization changing with changing technology. A. True B. False A microcomputer architecture and organization relationship is not very close. A. True B. False Changes in technology not only influence organization but also result in the introduction of more powerful and more complex architectures. A. True B. False The hierarchical nature of complex systems is essential to both their design and their description. A. True B. False Both the structure and functioning of a computer are, in essence, simple. A. True B. False A computer must be able to process, store, move, and control data. A. True B. False When data are moved over longer distances, to or from a remote device, the process is known as data transport. A. True B. False Computer technology is changing at a __________ pace. A. Slow B. Slow to medium C. Rapid D. Non-existent Computer _________ refers to those attributes that have a direct impact on the logical execution of a program. A. Organization B. Specifics C. Design D. Architecture Architectural attributes include __________ . A. I/O mechanisms B. Control signals C. Interfaces D. Memory technology used _________ attributes include hardware details transparent to the programmer. A. Interface B. Organizational C. Memory D. Architectural It is a(n) _________ design issue whether a computer will have a multiply instruction. A. Architectural B. Memory C. Elementary D. Organizational It is a(n) _________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system. A. Architectural B. Memory C. Mechanical D. Organizational A __________ system is a set of interrelated subsystems. A. Secondary B. Hierarchical C. Complex D. Functional An I/O device is referred to as a __________. A. CPU B. Control device C. Peripheral D. Register When data are moved over longer distances, to or from a remote device, the process is known as __________. A. Data communications B. Registering C. Structuring D. Data transport The _________ stores data. A. System bus B. I/O C. Main memory D. Control unit The __________ moves data between the computer and its external environment. A. Data transport B. I/O C. Register D. CPU interconnection A common example of system interconnection is by means of a __________. A. Register B. System bus C. Data transport D. Control device A _________ is a mechanism that provides for communication among CPU, main memory, and I/O. A. System interconnection B. CPU interconnection C. Peripheral D. Processor _________ provide storage internal to the CPU. A. Control units B. ALUs C. Main memory D. Registers The __________ performs the computer's data processing functions. A. Register B. CPU interconnection C. ALU D. System bus The world's first general-purpose electronic digital computer was designed and constructed at The Ohio State University. A. True B. False John Mauchly and John Eckert designed the ENIAC. A. True B. False The major drawback of the EDVAC was that it had to be programmed manually by setting switches and plugging and unplugging cables. A. True B. False The IAS is the prototype of all subsequent general-purpose computers. A. True B. False The IAS operates by repetitively performing an instruction cycle. A. True B. False Backward compatible means that the programs written for the older machines can be executed on the new machine. A. True B. False A vacuum tube is a solid-state device made from silicon. A. True B. False Computers are classified into generations based on the fundamental hardware technology employed. A. True B. False System software was introduced in the third generation of computers. A. True B. False A wafer is made of silicon and is broken up into chips which consists of many gates and/or memory cells plus a number of input and output attachment points. A. True B. False IBM's System/360 was the industry's first planned family of computers. A. True B. False Intel's 4004 was the first chip to contain all of the components of a CPU on a single chip. A. True B. False Designers wrestle with the challenge of balancing processor performance with that of main memory and other computer components. A. True B. False The Intel x86 evolved from RISC design principles and is used in embedded systems. A. True B. False A common measure of performance for a processor is the rate at which instructions are executed, expressed as billions of instructions per seconds (BIPS). A. True B. False The _________ was the world's first general-purpose electronic digital computer. A. UNIVAC B. MARK IV C. ENIAC D. Hollerith's Counting Machine The Electronic Numerical Integrator and Computer project was a response to U.S. needs during _________. A. The Civil War B. The French-American War C. World War I D. World War II The ENIAC used __________. A. Vacuum tubes B. Integrated circuits C. IAS D. Transistors The ENIAC is an example of a _________ generation computer. A. First B. Second C. Third D. Fourth The __________ interprets the instructions in memory and causes them to be executed. A. Main memory B. Control unit C. I/O D. Arithmetic and logic unit The memory of the IAS consists of 1000 storage locations called __________. A. Opcodes B. Wafers C. VLSIs D. Words The __________ contains the 8-bit opcode instruction being executed. A. Memory buffer register B. Instruction buffer register C. Instruction register D. Memory address register During the _________ the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR. A. Execute cycle B. Fetch cycle C. Instruction cycle D. Clock cycle Second generation computers used __________. A. Integrated circuits B. Transistors C. Vacuum tubes D. Large-scale integration The __________ defines the third generation of computers. A. Integrated circuit B. Vacuum tube C. Transistor D. VLSI The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance without increasing the clock rate. A. Multicore B. GPU C. Data channels D. MPC With the __________, Intel introduced the use of superscalar techniques that allow multiple instructions to execute in parallel. A. Core B. 8080 C. 80486 D. Pentium The __________ measures the ability of a computer to complete a single task. A. Clock speed B. Speed metric C. Execute cycle D. Cycle time ARM processors are designed to meet the needs of _________. A. Embedded real-time systems B. Application platforms C. Secure applications D. All of the above One increment, or pulse, of the system clock is referred to as a _________. A. Clock tick B. Cycle time C. Clock rate D. Cycle speed At a top level, a computer consists of CPU, memory, and I/O components. A. True B. False The basic function of a computer is to execute programs. A. True B. False Program execution consists of repeating the process of instruction fetch and instruction execution. A. True B. False Interrupts do not improve processing efficiency. A. True B. False An I/O module cannot exchange data directly with the processor. A. True B. False A key characteristic of a bus is that it is not a shared transmission medium. A. True B. False Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy. A. True B. False In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay. A. True B. False It is not possible to connect I/O controllers directly onto the system bus. A. True B. False The method of using the same lines for multiple purposes is known as time multiplexing. A. True B. False Timing refers to the way in which events are coordinated on the bus. A. True B. False With asynchronous timing the occurrence of events on the bus is determined by a clock. A. True B. False Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance. A. True B. False The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit. A. True B. False A key requirement for PCIe is high capacity to support the needs of higher data rate I/O devices such as Gigabit Ethernet. A. True B. False Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton. A. John Maulchy B. John von Neumann C. Herman Hollerith D. John Eckert The von Neumann architecture is based on which concept? A. Data and instructions are stored in a single read-write memory B. The contents of this memory are addressable by location C. Execution occurs in a sequential fashion D. All of the above A sequence of codes or instructions is called __________. A. Software B. Memory C. An interconnect D. A register The processing required for a single instruction is called a(n) __________ cycle. A. Execute B. Fetch C. Instruction D. Packet A(n) _________ is generated by a failure such as power failure or memory parity error. A. I/O interrupt B. Hardware failure interrupt C. Timer interrupt D. Program interrupt A(n) _________ is generated by some condition that occurs as a result of an instruction execution. A. Timer interrupt B. I/O interrupt C. Program interrupt D. Hardware failure interrupt The interconnection structure must support which transfer? A. Memory to processor B. Processor to memory C. I/O to or from memory D. All of the above A bus that connects major computer components (processor, memory, I/O) is called a __________. A. System bus B. Address bus C. Data bus D. Control bus The __________ are used to designate the source or destination of the data on the data bus. A. System lines B. Data lines C. Control lines D. Address lines The data lines provide a path for moving data among system modules and are collectively called the _________. A. Control bus B. Address bus C. Data bus D. System bus A __________ is the high-level set of rules for exchanging packets of data between devices. A. Bus B. Protocol C. Packet D. QPI Each data path consists of a pair of wires (referred to as a __________) that transmits data one bit at a time. A. Lane B. Path C. Line D. Bus The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer. A. Transaction layer B. Root layer C. Configuration layer D. Transport layer The TL supports which of the following address spaces? A. Memory B. I/O C. Message D. All of the above The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects. A. Link B. Protocol C. Routing D. Physical No single technology is optimal in satisfying the memory requirements for a computer system. A. True B. False A typical computer system is equipped with a hierarchy of memory subsystems, some internal to the system and some external. A. True B. False External memory is often equated with main memory. A. True B. False The processor requires its own local memory. A. True B. False Cache is not a form of internal memory. A. True B. False The unit of transfer must equal a word or an addressable unit. A. True B. False Both sequential access and direct access involve a shared read-write mechanism. A. True B. False In a volatile memory, information decays naturally or is lost when electrical power is switched off. A. True B. False To achieve greatest performance the memory must be able to keep up with the processor. A. True B. False Secondary memory is used to store program and data files and is usually visible to the programmer only in terms of individual bytes or words. A. True B. False The L1 cache is slower than the L3 cache. A. True B. False With write back updates are made only in the cache. A. True B. False It has become possible to have a cache on the same chip as the processor. A. True B. False All of the Pentium processors include two on-chip L1 caches, one for data and one for instructions. A. True B. False Cache design for HPC is the same as that for other hardware platforms and applications. A. True B. False __________ refers to whether memory is internal or external to the computer. A. Location B. Access C. Hierarchy D. Tag Internal memory capacity is typically expressed in terms of _________. A. Hertz B. Nanos C. Bytes D. LOR For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module. A. Access time B. Unit of transfer C. Capacity D. Memory ratio "Memory is organized into records and access must be made in a specific linear sequence" is a description of __________. A. Sequential access B. Direct access C. Random access D. Associative individual blocks or records have a unique address based on physical location with __________. A. Associative B. Physical access C. Direct access D. Sequential access For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use. A. Memory cycle time B. Direct access C. Transfer rate D. Access time The ________ consists of the access time plus any additional time required before a second access can commence. A. Latency B. Memory cycle time C. Direct access D. Transfer rate A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________. A. Disk cache B. Latency C. Virtual address D. Miss A line includes a _________ that identifies which particular block is currently being stored. A. Cache B. Hit C. Tag D. Locality __________ is the simplest mapping technique and maps each block of main memory into only one possible cache line. A. Direct mapping B. Associative mapping C. Set associative mapping D. None of the above When using the __________ technique all write operations made to main memory are made to the cache as well. A. Write back B. LRU C. Write through D. Unified cache The key advantage of the __________ design is that it eliminates contention for the cache between the instruction fetch/decode unit and the execution unit. A. Logical cache B. Split cache C. Unified cache D. Physical cache The Pentium 4 _________ component executes micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers. A. Fetch/decode unit B. Out-of-order execution logic C. Execution unit D. Memory subsystem In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory. A. Miss B. Hit C. Line D. Tag A logical cache stores data using __________. A. Physical addresses B. Virtual addresses C. Random addresses D. None of the above The basic element of a semiconductor memory is the memory cell. A. True B. False A characteristic of ROM is that it is volatile. A. True B. False RAM must be provided with a constant power supply. A. True B. False The two traditional forms of RAM used in computers are DRAM and SRAM. A. True B. False A static RAM will hold its data as long as power is supplied to it. A. True B. False Nonvolatile means that power must be continuously supplied to the memory to preserve the bit values. A. True B. False The advantage of RAM is that the data or program is permanently in main memory and need never be loaded from a secondary storage device. A. True B. False Semiconductor memory comes in packaged chips. A. True B. False All DRAMs require a refresh operation. A. True B. False A number of chips can be grouped together to form a memory bank. A. True B. False An error-correcting code enhances the reliability of the memory at the cost of added complexity. A. True B. False DRAM is much costlier than SRAM. A. True B. False RDRAM is limited by the fact that it can only send data to the processor once per bus clock cycle. A. True B. False The prefetch buffer is a memory cache located on the RAM chip. A. True B. False The SRAM on the CDRAM cannot be used as a buffer to support the serial access of a block of data. A. True B. False Which properties do all semiconductor memory cells share? A. They exhibit two stable states which can be used to represent binary 1 and 0 B. They are capable of being written into to set the state C. They are capable of being read to sense the state D. All of the above One distinguishing characteristic of memory that is designated as _________ is that it is possible to both to read data from the memory and to write new data into the memory easily and rapidly. A. RAM B. ROM C. EPROM D. EEPROM Which of the following memory types are nonvolatile? A. Erasable PROM B. Programmable ROM C. Flash memory D. All of the above In a _________, binary values are stored using traditional flip-flop logic-gate configurations. A. ROM B. SRAM C. DRAM D. RAM A __________ contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new data written into it. A. RAM B. SRAM C. ROM D. Flash memory With _________ the microchip is organized so that a section of memory cells are erased in a single action. A. Flash memory B. SDRAM C. DRAM D. EEPROM __________ can be caused by harsh environmental abuse, manufacturing defects, and wear. A. SEC errors B. Hard errors C. Syndrome errors D. Soft errors _________ can be caused by power supply problems or alpha particles. A. Soft errors B. AGT errors C. Hard errors D. SEC errors The _________ exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states. A. DDR-DRAM B. SDRAM C. CDRAM D. None of the above ________ can send data to the processor twice per clock cycle. A. CDRAM B. SDRAM C. DDR-DRAM D. RDRAM __________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip. A. DDR2 B. RDRAM C. CDRAM D. DDR3 ________ increases the prefetch buffer size to 8 bits. A. CDRAM B. RDRAM C. DDR3 D. All of the above Theoretically, a DDR module can transfer data at a clock rate in the range of __________ MHz. A. 200 to 600 B. 400 to 1066 C. 600 to 1400 D. 800 to 1600 A DDR3 module transfers data at a clock rate of __________ MHz. A. 600 to 1200 B. 800 to 1600 C. 1000 to 2000 D. 1500 to 3000 The ________ enables the RAM chip to preposition bits to be placed on the data bus as rapidly as possible. A. Flash memory B. Hamming code C. RamBus D. Buffer Magnetic disks are the foundation of external memory on virtually all computer systems. A. True B. False During a read or write operation, the head rotates while the platter beneath it stays stationary. A. True B. False The width of a track is double that of the head. A. True B. False There are typically hundreds of sectors per track and they may be either fixed or variable lengths. A. True B. False A bit near the center of a rotating disk travels past a fixed point slower than a bit on the outside. A. True B. False The disadvantage of using CAV is that individual blocks of data can only be directly addressed by track and sector. A. True B. False A removable disk can be removed and replaced with another disk. A. True B. False The head must generate or sense an electromagnetic field of sufficient magnitude to write and read properly. A. True B. False The transfer time to or from the disk does not depend on the rotation speed of the disk. A. True B. False RAID is a set of physical disk drives viewed by the operating system as a single logical drive. A. True B. False RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve performance. A. True B. False Because data are striped in very small strips, RAID 3 cannot achieve very high data transfer rates. A. True B. False The SSDs now on the market use a type of semiconductor memory referred to as flash memory. A. True B. False SSD performance has a tendency to speed up as the device is used. A. True B. False Flash memory becomes unusable after a certain number of writes. A. True B. False Greater ability to withstand shock and damage, improvement in the uniformity of the magnet film surface to increase disk reliability, and a significant reduction in overall surface defects to help reduce read-write errors, are all benefits of ___________. a. magnetic read and write mechanisms b. platters c. the glass substrate d. a solid state drive Adjacent tracks are separated by _________. a. sectors b. gaps c. pits d. heads Data are transferred to and from the disk in __________. a. tracks b. gaps c. sectors d. pits In most contemporary systems fixed-length sectors are used, with _________ bytes being the nearly universal sector size. a. 64 b. 128 c. 256 d. 512 Scanning information at the same rate by rotating the disk at a fixed speed is known as the _________. a. constant angular velocity b. magnetoresistive c. rotational delay d. constant linear velocity The disadvantage of _________ is that the amount of data that can be stored on the long outer tracks is only the same as what can be stored on the short inner tracks. a. SSD b. CAV c. ROM d. CLV A __________ disk is permanently mounted in the disk drive, such as the hard disk in a personal computer. a. nonremovable b. movable-head c. double sided d. removable When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________. a. multiple sided b. substrate c. double sided d. all of the above The set of all the tracks in the same relative position on the platter is referred to as a _________. a. floppy disk b. single-sided disk c. sector d. cylinder The sum of the seek time and the rotational delay equals the _________, which is the time it takes to get into position to read or write. a. access time b. gap time c. transfer time d. constant angular velocity __________ is the standardized scheme for multiple-disk database design. a. RAID b. CAV c. CLV d. SSD RAID level ________ has the highest disk overhead of all RAID types. a. 0 b. 1 c. 3 d. 5 A _________ is a high-definition video disk that can store 25 Gbytes on a single layer on a single side. a. DVD b. DVD-R c. DVD-RW d. Blu-ray DVD ________ is when the disk rotates more slowly for accesses near the outer edge than for those near the center. a. Constant angular velocity (CAV) b. Magnetoresistive c. Constant linear velocity (CLV) d. Seek time The areas between pits are called _________. a. lands b. sectors c. cylinders d. strips A set of I/O modules is a key element of a computer system. A. True B. False An I/O module must recognize one unique address for each peripheral it controls. A. True B. False I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes. A. True B. False It is the responsibility of the processor to periodically check the status of the I/O module until it finds that the operation is complete. A. True B. False With isolated I/O there is a single address space for memory locations and I/O devices. A. True B. False A disadvantage of memory-mapped I/O is that valuable memory address space is used up. A. True B. False The disadvantage of the software poll is that it is time consuming. A. True B. False With a daisy chain the processor just picks the interrupt line with the highest priority. A. True B. False Bus arbitration makes use of vectored interrupts. A. True B. False The rotating interrupt mode allows the processor to inhibit interrupts from certain devices. A. True B. False Because the 82C55A is programmable via the control register, it can be used to control a variety of simple peripheral devices. A. True B. False When large volumes of data are to be moved, a more efficient technique is direct memory access (DMA). A. True B. False An I/O channel has the ability to execute I/O instructions, which gives it complete control over I/O operations. A. True B. False A multipoint external interface provides a dedicated line between the I/O module and the external device. A. True B. False A Thunderbolt compatible peripheral interface is no more complex than that of a simple USB device. A. True B. False The _________ contains logic for performing a communication function between the peripheral and the bus. A. I/O channel B. I/O module C. I/O processor D. I/O command The most common means of computer/user interaction is a __________. A. keyboard/monitor B. mouse/printer C. modem/printer D. monitor/printer The I/O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices. A. cycle B. status reporting C. control and timing D. data An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually referred to as an _________. A. I/O channel B. I/O command C. I/O controller D. device controller An I/O module that is quite primitive and requires detailed control is usually referred to as an _________. A. I/O command B. I/O controller C. I/O channel D. I/O processor The _________ command causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral. A. control B. test C. read D. write The ________ command is used to activate a peripheral and tell it what to do. A. control B. test C. read D. write ________ is when the DMA module must force the processor to suspend operation temporarily. A. Interrupt B. Thunderbolt C. Cycle stealing D. Lock down The 8237 DMA is known as a _________ DMA controller. A. command B. cycle stealing C. interrupt D. fly-by ________ is a digital display interface standard now widely adopted for computer monitors, laptop displays, and other graphics and video interfaces. A. DisplayPort B. PCI Express C. Thunderbolt D. InfiniBand The ________ layer is the key to the operation of Thunderbolt and what makes it attractive as a high-speed peripheral I/O technology. A. cable B. application C. common transport D. physical The Thunderbolt protocol _________ layer is responsible for link maintenance including hot-plug detection and data encoding to provide highly efficient data transfer. A. cable B. application C. common transport D. physical The ________ contains I/O protocols that are mapped on to the transport layer. A. cable B. application C. common transport D. physical A ________ is used to connect storage systems, routers, and other peripheral devices to an InfiniBand switch. A. target channel adapter B. InfiniBand switch C. host channel adapter D. subnet A ________ connects InfiniBand subnets, or connects an InfiniBand switch to a network such as a local area network, wide area network, or storage area network. A. memory controller B. TCA C. HCA D. router Scheduling and memory management are the two OS functions that are most relevant to the study of computer organization and architecture. A. True B. False The end user is concerned mainly with the computer's architecture. A. True B. False The most important system program is the OS. A. True B. False The ABI is the boundary between hardware and software. A. True B. False The OS must determine how much processor time is to be devoted to the execution of a particular user program. A. True B. False With a batch operating system the user does not have direct access to the processor. A. True B. False Privileged instructions are certain instructions that are designated special and can be executed only by the monitor. A. True B. False Uniprogramming is the central theme of modern operating systems. A. True B. False Both batch multiprogramming and time sharing use multiprogramming. A. True B. False An interrupt is a hardware-generated signal to the processor. A. True B. False Swapping is an I/O operation. A. True B. False With demand paging it is necessary to load an entire process into main memory. A. True B. False The Pentium II includes hardware for both segmentation and paging. A. True B. False ARM provides a versatile virtual memory system architecture that can be tailored to the needs of the embedded system designer. A. True B. False Managers are users of domains that must observe the access permissions of the individual sections and/or pages that make up that domain. A. True B. False The __________ is a program that controls the execution of application programs and acts as an interface between applications and the computer hardware. A. job control language B. operating system C. batch system D. nucleus Facilities and services provided by the OS that assist the programmer in creating programs are in the form of _________ programs that are not actually part of the OS but are accessible through the OS. A. utility B. multitasking C. JCL D. logical address The _________ defines the repertoire of machine language instructions that a computer can follow. A. ABI B. API C. HLL D. ISA The _________ defines the system call interface to the operating system and the hardware resources and services available in a system through the user instruction set architecture. A. HLL B. API C. ABI D. ISA The ________ gives a program access to the hardware resources and services available in a system through the user instruction set architecture supplemented with high-level language library calls. A. JCL B. ISA C. ABI D. API A _________ system works only one program at a time. A. batch B. uniprogramming C. kernel D. privileged instruction A _________ is a special type of programming language used to provide instructions to the monitor. A. job control language B. multiprogram C. kernel D. utility The _________ scheduler determines which programs are admitted to the system for processing. A. long-term B. medium-term C. short-term D. I/O The ________ scheduler is also known as the dispatcher. A. long-term B. medium-term C. short-term D. I/O A _________ is an actual location in main memory. A. logical address B. partition address C. base address D. physical address ________ is when the processor spends most of its time swapping pages rather than executing instructions. A. Swapping B. Thrashing C. Paging D. Multitasking Virtual memory schemes make use of a special cache called a ________ for page table entries. A. TLB B. HLL C. VMC D. SPB With _________ the virtual address is the same as the physical address. A. unsegmented unpaged memory B. unsegmented paged memory C. segmented unpaged memory D. segmented paged memory A _________ is a collection of memory regions. A. APX B. nucleus C. domain D. page table The OS maintains a __________ for each process that shows the frame location for each page of the process. A. kernel B. page table C. TLB D. logical address Our primary counting system is based on binary digits to represent numbers. A. True B. False The decimal system has a radix of 100. A. True B. False Negative powers of 10 are used to represent the positions of the numbers for decimal fractions. A. True B. False A number with both an integer and fractional part has digits raised to both positive and negative powers of 10. A. True B. False In any number, the rightmost digit is referred to as the most significant digit. A. True B. False A number cannot be converted from binary notation to decimal notation. A. True B. False There are 50 tens in the number 509. A. True B. False The decimal system is a special case of a positional number system with radix 10 and with digits in the range 0 through 9. A. True B. False Although convenient for computers, the binary system is exceedingly cumbersome for human beings. A. True B. False A nibble is a grouping of four decimal digits. A. True B. False Hexadecimal notation is only used for representing integers. A. True B. False It is extremely easy to convert between binary and hexadecimal notation. A. True B. False Hexadecimal notation is more compact than binary notation. A. True B. False A sequence of hexadecimal digits can be thought of as representing an integer in base 10. A. True B. False Because of the inherent binary nature of digital computer components, all forms of data within computers are represented by various binary codes. A. True B. False The decimal system has a base of _________. A. 0 B. 10 C. 100 D. 1000 Which digit represents "hundreds" in the number 8732? A. 8 B. 7 C. 3 D. 2 Which of the following is correct? A. 25 = (2 x 10^2) + (5 x 10^1) B. 289 = (2 x 10^3) + (8 x 10^1) + (9 x 10^0) C. 7523 = (7 x 10^3) + (5 x 10^2) + (2 x 10^1) + (3 x 10^0) D. 0.628 = (6 x 10^-3) + (2 x 10^-2) + (8 x 10^-1) In the number 3109, the 3 is referred to as the _________. A. most significant digit B. least significant digit C. radix D. base In the number 3109, the 9 is referred to as the _________. A. most significant digit B. least significant digit C. radix D. base Numbers in the binary system are represented to the _________. A. base 0 B. base 1 C. base 2 D. base 10 Hexadecimal has a base of _________. A. 2 B. 8 C. 10 D. 16 The binary string 001 is equivalent to __________. A. DE1 (16) B. C78 (16) C. FF64 (16) D. B8F (16) The _________ system uses only the numbers 0 and 1. A. positional B. binary C. hexadecimal D. decimal Decimal "10" is __________ in binary. A. 1000 B. 0010 C. 1010 D. 0001 Decimal "10" is _________ in hexadecimal. A. 1 B. A C. 0 D. FF Four bits is called a _________. A. radix point B. byte C. nibble D. binary digit Another term for "base" is __________. A. radix B. integer C. position D. digit In the number 472.156 the 2 is the _________. A. most significant digit B. radix point C. least significant digit D. none of the above Binary 0101 is hexadecimal _________. A. 0 B. 5 C. A D. 10 One drawback of sign-magnitude representation is that there are two representations of 0. Both sign-magnitude representation and twos complement representation use the most significant bit as a sign bit. It is not necessary for the ALU to signal when overflow occurs. Overflow can only occur if there is a carry. Compared with addition and subtraction, multiplication is a complex operation, whether performed in hardware of software. For each 1 on the multiplier, an add and a shift operation are required; but for each 0 only a shift is required. Addition and subtraction can be performed on numbers in twos complement notation by treating them as unsigned integers. Booth's algorithm performs more additions and subtractions than a straightforward algorithm. With a fixed-point notation it is possible to represent a range of positive and negative integers centered on or near 0. An advantage of biased representation is that nonnegative floating-point numbers can be treated as integers for comparison purposes. For base 2 representation, a normal number is one in which the most significant bit of the significand is zero. Actual floating-point representations include a special bit pattern to designate zero. The numbers represented in floating-point notation are not spaced evenly along the number line, as are fixed-point numbers. Overflow is a less serious problem because the result can generally be satisfactorily approximated by 0. One of the trade-offs of floating-point math is that many calculations produce results that are not exact and have to be rounded to the nearest value that the notation can represent. twos complement representation {ANS)- The most common scheme in implementing the integer portion of the ALU is: a. sign-magnitude representation b. biased representation c. twos complement representation d. ones complement representation Twos complimen __________ representation is almost universally used as the processor representation for integers. a. Biased b. Twos compliment c. Sign-magnitude d. Decimal sign extension {ANS)- Moving the sign bit to the new leftmost position and filling in with copies of the sign bit is called _________. a. sign extension b. range extension c. bit extension d. partial extension sign-magnitude {ANS)- In ________ representation the rule for forming the negation of an integer is to invert the sign bit. a. ones complement b. twos complement c. biased d. sign-magnitude Overflow {ANS)- ________ is when the result may be larger than can be held in the word size being used. a.Overflow b. Arithmetic shift c. Underflow d. Partial product Multiplication {ANS)- __________ involves the generation of partial products, one for each digit in the multiplier, which are then summed to produce the final product. a. Addition b. Subtraction c. Multiplication d. Division mantiss Although considered obsolete, the term _________ is sometimes used instead of significand. a. minuend b. mantissa c. base d. subtrahend negative overflow {ANS)- Negative numbers less than -(2 - 2^-23) x 2 128 are called _________. a. positive underflow b. positive overflow c. negative underflow d. negative overflow negative underflow {ANS)- Negative numbers greater than 2^-127 are called _________. a. negative overflow b. negative underflow c. positive overflow d. positive underflow positive underflow {ANS)- Positive numbers less than 2^-127 are called ________. a. positive underflow b. positive overflow c. negative underflow d. negative overflow positive overflow {ANS)- Positive numbers greater than (2 - 2^-23) x 2^-128 are called _________. a. negative underflow b. positive overflow c. positive underflow d. negative overflow Extended precision {ANS)- _________ formats extend a supported basic format by providing additional bits in the exponent and in the significand. a. Arithmetic b. Basic c. Extended precision d. Interchange Subnormal numbers {ANS)- _________ are included in IEEE 754 to handle cases of exponent underflow. a. Subnormal numbers b. Guard bits c. Normal numbers d. Radix points Exponent overflow {ANS)- __________ is when a positive exponent exceeds the maximum possible exponent value. a. Significand underflow b. Significand overflow c. Exponent overflow d. Exponent underflow Exponent underflow {ANS)- __________ means that the number is too small to be represented and it may be reported as 0. a. Negative underflow b. Exponent underflow c. Positive underflow d. Significand underflow The operation of the digital computer is based on the storage and processing of binary data. A. True B. False Claude Shannon, a research assistant in the Electrical Engineering Department at M.I.T., proposed the basic principles of Boolean algebra. A. True B. False In the absence of parentheses, the AND operation takes precedence over the OR operation. A. True B. False Logical functions are implemented by the interconnection of decoders. A. True B. False The delay by the propagation time of signals through the gate is known as the gate delay. A. True B. False A combinational circuit consists of n binary inputs and m binary outputs. A. True B. False Any Boolean function can be implemented in electronic form as a network of gates. A. True B. False A Boolean function can be realized in the sum of products (SOP) form but not in the product of sums (POS) form. A. True B. False "Don't care" conditions are when certain combinations of values of variables never occur, and therefore the corresponding output never occurs. A. True B. False The value to be loaded into the program counter can come from a binary counter, the instruction register, or the output of the ALU. A. True B. False In general, a decoder has n inputs and 2^n outputs. A. True B. False Combinational circuits are often referred to as "memoryless" circuits because their output depends only on their current input and no history of prior inputs is retained. A. True B. False Binary addition is exactly the same as Boolean algebra. A. True B. False Events in the digital computer are synchronized to a clock pulse so that changes occur only when a clock pulse occurs. A. True B. False A register is a digital circuit used within the CPU to store one or more bits of data. A. True B. False The operand ________ yields true if and only if both of its operands are true. A. XOR B. OR C. AND D. NOT The operation _________ yields true if either or both of its operands are true. A. NOT B. AND C. NAND D. OR The unary operation _________ inverts the value of its operand. A. OR B. NOT C. NAND D. XOR A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals. A. gate B. decoder C. counter D. flip-flop Which of the following is a functionally complete set? A. AND, NOT B. NOR C. AND, OR, NOT D. all of the above For more than four variables an alternative approach is a tabular technique referred to as the _________ method. A. DeMorgan B. Quine-McCluskey C. Karnaugh map D. Boole-Shannon ________ are used in digital circuits to control signal and data routing. A. Multiplexers B. Program counters C. Flip-flops D. Gates ________ is implemented with combinational circuits. A. Nano memory B. Random access memory C. Read only memory D. No memory The ________ exists in one of two states and, in the absence of input, remains in that state. A. assert B. complex PLD C. decoder D. flip-flop The ________ flip-flop has two inputs and all possible combinations of input values are valid. A. J-K B. D C. S-R D. clocked S-R A _________ accepts and/or transfers information serially. A. S-R latch B. shift register C. FPGA D. parallel register Counters can be designated as _________. A. asynchronous B. synchronous C. both asynchronous and synchronous D. neither asynchronous or synchronous CPUs make use of _________ counters, in which all of the flip-flops of the counter change at the same time. A. synchronous B. asynchronous C. clocked S-R D. timed ripple The _________ table provides the value of the next output when the inputs and the present output are known, which is exactly the information needed to design the counter or any sequential circuit. A. excitation B. Kenough C. J-K flip-flop D. FPGA A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and a higher ration of flip-flops to logic resources than do CPLDs. A. SPLD B. FPGA C. PAL D. PLA One boundary where the computer designer and the computer programmer can view the same machine is the machine instruction set. A. True B. False The operation to be performed is specified by a binary code known as the operation code. A. True B. False The address of the next instruction to be fetched must be a real address, not a virtual address. A. True B. False It has become common practice to use a symbolic representation of machine instructions. A. True B. False A high-level language expresses operations in a basic form involving the movement of data to or from registers. A. True B. False One of the traditional ways of describing processor architecture is in terms of the number of addresses contained in each instruction. A. True B. False Memory references are faster than register references. A. True B. False The instruction set is the programmer's means of controlling the processor. A. True B. False Addresses are a form of data. A. True B. False Not all machine languages include numeric data types. A. True B. False ARM processors support data types of 8 (byte), 16 (halfword), and 32 (word) bits in length. A. True B. False Most machines provide the basic arithmetic operations of add, subtract, multiply, and divide. A. True B. False A branch can be either forward or backward. A. True B. False Procedures do not allow programming tasks to be subdivided into smaller units. A. True B. False The focus of MMX technology is multimedia programming. A. True B. False The ________ specifies the operation to be performed. A. source operand reference B. opcode C. next instruction reference D. processor register A(n) _________ expresses operations in a concise algebraic form using variables. A. opcode B. high-level language C. machine language D. register There must be ________ instructions for moving data between memory and the registers. A. branch B. logic C. memory D. I/O ________ instructions operate on the bits of a word as bits rather than as numbers, providing capabilities for processing any other type of data the user may wish to employ. A. Logic B. Arithmetic C. Memory D. Test _________ instructions provide computational capabilities for processing number data. A. Boolean B. Logic C. Memory D. Arithmetic _______ instructions are needed to transfer programs and data into memory and the results of computations back out to the user. A. I/O B. Transfer C. Control D. Branch The x86 data type that is a signed binary value contained in a byte, word, or doubleword, using twos complement representation is _________. A. general B. ordinal C. integer D. packed BCD The most fundamental type of machine instruction is the _________ instruction. A. conversion B. data transfer C. arithmetic D. logical The _________ instruction includes an implied address. A. skip B. rotate C. stack D. push Which of the following is a true statement? A. a procedure can be called from more than one location B. a procedure call can appear in a procedure C. each procedure call is matched by a return in the called program D. all of the above The entire set of parameters, including return address, which is stored for a procedure invocation is referred to as a _________. A. branch B. stack frame C. pop D. push Which ARM operation category includes logical instructions (AND, OR, XOR), add and subtract instructions, and test and compare instructions? A. data-processing instructions B. branch instructions C. load and store instructions D. extend instructions In the ARM architecture only _________ instructions access memory locations. A. data processing B. status register access C. load and store D. branch Which data type is defined in MMX? A. packed byte B. packed word C. packed doubleword D. all of the above A branch instruction in which the branch is always taken is _________. A. conditional branch B. unconditional branch C. jump D. bi-endian The value of the mode field determines which addressing mode is to be used. A. True B. False In a system without virtual memory, the effective address is a virtual address or a register. A. True B. False The disadvantage of immediate addressing is that the size of the number is restricted to the size of the address field. A. True B. False With direct addressing, the length of the address field is usually less than the word length, thus limiting the address range. A. True B. False Register addressing is similar to direct addressing with the only difference being that the address field refers to a register rather than a main memory address. A. True B. False Register indirect addressing uses the same number of memory references as indirect addressing. A. True B. False Three of the most common uses of stack addressing are relative addressing, base-register addressing, and indexing. A. True B. False The method of calculating the EA is the same for both base-register addressing and indexing. A. True B. False Typically an instruction set will include both preindexing and postindexing. A. True B. False The x86 is equipped with a variety of addressing modes intended to allow the efficient execution of high-level languages. A. True B. False The base with index and displacement mode sums the contents of the base register, the index register, and a displacement to form the effective address. A. True B. False The memory transfer rate has not kept up with increases in processor speed. A. True B. False For addresses that reference memory the range of addresses that can be referenced is not related to the number of address bits. A. True B. False The principal price to pay for variable-length instructions is an increase in the complexity of the processor. A. True B. False One advantage of linking the addressing mode to the operand rather than the opcode is that any addressing mode can be used with any opcode. A. True B. False The advantage of __________ is that no memory reference other than the instruction fetch is required to obtain the operand. A. direct addressing B. immediate addressing C. register addressing D. stack addressing The principal advantage of ___________ addressing is that it is a very simple form of addressing. A. displacement B. register C. stack D. direct __________ has the advantage of large address space, however it has the disadvantage of multiple memory references. A. Indirect addressing B. Direct addressing C. Immediate addressing D. Stack addressing The advantages of _________ addressing are that only a small address field is needed in the instruction and no time-consuming memory references are required. A. direct B. indirect C. register D. displacement __________ has the advantage of flexibility, but the disadvantage of complexity. A. Stack addressing B. Displacement addressing C. Direct addressing D. Register addressing For _________, the address field references a main memory address and the referenced register contains a positive displacement from that address. A. indexing B. base-register addressing C. relative addressing D. all of the above Indexing performed after the indirection is __________. A. relative addressing B. autoindexing C. postindexing D. preindexing For the _________ mode, the operand is included in the instruction. A. immediate B. base C. register D. displacement The only form of addressing for branch instructions is _________ addressing. A. register B. relative C. base D. immediate Which of the following interrelated factors go into determining the use of the addressing bits? A. number of operands B. number of register sets C. address range D. all of the above _________ is a principle by which two variables are independent of each other. A. Opcode B. Orthogonality C. Completeness D. Autoindexing The _________ was designed to provide a powerful and flexible instruction set within the constraints of a 16-bit minicomputer. A. PDP-1 B. PDP-8 C. PDP-11 D. PDP-10 The __________ byte consists of three fields: the Scale field, the Index field and the Base field. A. SIB B. VAX C. PDP-11 D. ModR/M All instructions in the ARM architecture are __________ bits long and follow a regular format. A. 8 B. 16 C. 32 D. 64 __________ is a design principle employed in designing the PDP-10 instruction set. A. Orthogonality B. Completeness C. Direct addressing D. All of the above The processor needs to store instructions and data temporarily while an instruction is being executed. A. True B. False The control unit (CU) does the actual computation or processing of data. A. True B. False Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy. A. True B. False Condition codes facilitate multiway branches. A. True B. False The allocation of control information between registers and memory are not considered to be a key design issue. A. True B. False Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity. A. True B. False The cycle time of an instruction pipeline is the time needed to advance a set of instructions one stage through the pipeline. A. True B. False A control hazard occurs when two or more instructions that are already in the pipeline need the same resource. A. True B. False One of the major problems in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline. A. True B. False The predict-never-taken approach is the most popular of all the branch prediction methods. A. True B. False It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired. A. True B. False Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions can be serviced and later resumed. A. True B. False An interrupt is generated from software and it is provoked by the execution of an instruction. A. True B. False While the processor is in user mode the program being executed is unable to access protected system resources or to change mode, other than by causing an exception to occur. A. True B. False The exception modes have full access to system resources and can change modes freely. A. True B. False __________ are a set of storage locations. A. Processors B. PSWs C. Registers D. Control units The ________ controls the movement of data and instructions into and out of the processor. A. control unit B. ALU C. shifter D. branch ________ registers may be used only to hold data and cannot be employed in the calculation of an operand address. A. General purpose B. Data C. Address D. Condition code __________ are bits set by the processor hardware as the result of operations. A. MIPS B. Condition codes C. Stacks D. PSWs The _________ contains the address of an instruction to be fetched. A. instruction register B. memory address register C. memory buffer register D. program counter The _________ contains a word of data to be written to memory or the word most recently read. A. MAR B. PC C. MBR D. IR The ________ determines the opcode and the operand specifiers. A. decode instruction B. fetch operands C. calculate operands D. execute instruction _________ is a pipeline hazard. A. Control B. Resource C. Data D. All of the above A ________ hazard occurs when there is a conflict in the access of an operand location. A. resource B. data C. structural D. control A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence. A. loop buffer B. delayed branch C. multiple stream D. branch prediction The _________ is a small cache memory associated with the instruction fetch stage of the pipeline. A. dynamic branch B. loop table C. branch history table D. flag The _________ stage includes ALU operations, cache access, and register update. A. decode B. execute C. fetch D. write back ________ is used for debugging. A. Direction flag B. Alignment check C. Trap flag D. Identification flag The ARM architecture supports _______ execution modes. A. 2 B. 8 C. 11 D. 7 The OS usually runs in ________. A. supervisor mode B. abort mode C. undefined mode D. fast interrupt mode Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept. A. True B. False Pipelining is a means of introducing parallelism into the essentially sequential nature of a machine-instruction program. A. True B. False The major cost in the life cycle of a system is hardware. A. True B. False It is common for programs, both system and application, to continue to exhibit new bugs after years of operation. A. True B. False Procedure calls and returns are not important aspects of HLL programs. A. True B. False The register file is on the same chip as the ALU and control unit. A. True B. False The register file employs much shorter addresses than addresses for cache and memory. A. True B. False To handle any possible pattern of calls and returns the number of register windows would have to be unbounded. A. True B. False Cache memory is a much faster memory than the register file. A. True B. False The cache is capable of handling global as well as local variables. A. True B. False With simple, one cycle instructions, there is little or no need for microcode. A. True B. False When using graph coloring, nodes that share the same color cannot be assigned to the same register. A. True B. False Almost all RISC instructions use simple register addressing. A. True B. False RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations. A. True B. False Unrolling can improve performance by increasing instruction parallelism by improving pipeline performance. A. True B. False _________ determines the control and pipeline organization. A. Calculation B. Execution sequencing C. Operations performed D. Operands used The Patterson study examined the dynamic behavior of _________ programs, independent of the underlying architecture. A. HLL B. RISC C. CISC D. all of the above _________ is the fastest available storage device. A. Main memory B. Cache C. Register storage D. HLL The first commercial RISC product was _________. A. SPARC B. CISC C. VAX D. the Pyramid _________ instructions are used to position quantities in registers temporarily for computational operations. A. Load-and-store B. Window C. Complex D. Branch Which stage is required for load and store operations? A. I B. E C. D D. all of the above A ________ instruction can be used to account for data and branch delays. A. SUB B. NOOP C. JUMP D. all of the above The instruction location immediately following the delayed branch is referred to as the ________. A. delay load B. delay file C. delay slot D. delay register A tactic similar to the delayed branch is the _________, which can be used on LOAD instructions. A. delayed load B. delayed program C. delayed slot D. delayed register The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses, registers, and the ALU. A. 16 B. 32 C. 64 D. 128 All MIPS R series processor instructions are encoded in a single ________ word format. A. 4-bit B. 8-bit C. 16-bit D. 32-bit A _________ architecture is one that makes use of more, and more fine-grained pipeline stages. A. parallel B. superpipelined C. superscalar D. hybrid The R4000 can have as many as _______ instructions in the pipeline at the same time. A. 8 B. 10 C. 5 D. 3 SPARC refers to an architecture defined by ________. A. Microsoft B. Apple C. Sun Microsystems D. IBM The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage. A. write back B. tag check C. data cache D. instruction execute The superscalar approach has now become the standard method for implementing high-performance microprocessors. A. True B. False In a traditional scalar organization there is a single pipelined functional unit for integer operations and one for floating-point operations. A. True B. False In the scalar organization there are multiple functional units, each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure. A. True B. False The superscalar approach depends on the ability to execute multiple instructions in parallel. A. True B. False True data dependency is also called flow dependency or read after write (RAW) dependency. A. True B. False Resources include: memories, caches, buses, and register-file ports. A. True B. False Machine parallelism exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping. A. True B. False The simplest instruction issue policy is to issue instructions in the exact order that would be achieved by sequential execution (in-order issue) and to write results in that same order (in-order completion). A. True B. False In-order completion requires more complex instruction issue logic than out-of-order completion. A. True B. False The reorder buffer is temporary storage for results completed out of order that are then committed to the register file in program order. A. True B. False Register renaming eliminates antidependencies and output dependencies. A. True B. False In effect, the Pentium 4 architecture implements a CISC instruction set architecture on a RISC microarchitecture. A. True B. False The schedulers are responsible for retrieving micro-ops from the micro-op queues and dispatching these for execution. A. True B. False ARM architecture has yet to implement superscalar techniques in the instruction pipeline. A. True B. False The Cortex-A8 targets a wide variety of mobile and consumer applications including mobile phones, set-top boxes, gaming consoles and automotives navigation/entertainment systems. A. True B. False The superscalar approach can be used on __________ architecture. A. RISC B. CISC C. neither RISC nor CISC D. both RISC and CISC The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines. A. scalar B. branch C. superscalar D. flow dependency Which of the following is a fundamental limitation to parallelism with which the system must cope? A. procedural dependency B. resource conflicts C. antidependency D. all of the above The situation where the second instruction needs data produced by the first instruction to execute is referred to as __________. A. true data dependency B. output dependency C. procedural dependency D. antidependency The instructions following a branch have a _________ on the branch and cannot be executed until the branch is executed. A. resource dependency B. procedural dependency C. output dependency D. true data dependency ________ refers to the process of initiating instruction execution in the processor's functional units. A. Instruction issue B. In-order issue C