USN
Advanced Digital Logic Verification
Time: 3 Hours Max. Marks: 100
Instructions: 1. Answer any one full question from each of the units.
2. Assume suitable missing data, if any.
3. Draw neat diagrams, wherever necessary
UNIT - I L CO PO M
1 a. Explain the basic testbench functionality
(2) (1) (1) (4)
b. Briefly explain functional coverage with diagrams.
(2) (1) (1) (8)
c. Interpret the different design inputs that should be randomized while generating stimulus for a
design .
(2) (1) (1) (8)
OR
2 a. Explain the different levels of testing in verification process
(2) (1) (1) (4)
b. Briefly explain directed testing with diagrams
(2) (1) (1) (8)
c. Explain typical verification flow with flow chart.
(2) (1) (1) (8)
UNIT – II L CO PO M
3 a. Write a system verilog code to illustrate different operations performed on queues.
( 4 ) ( 2 ) ( 3 ) (10)
b. Write the syntax of clocking blocks in system verilog and explain.
( 3 ) ( 2 ) ( 1 ) (10)
OR
4 a. Identify the differences between dynamic arrays and associative arrays in system verilog with
example
( 4 ) ( 2 ) ( 3 ) (10)
b. Illustrste the following operations performed on single dimensional fixed size arrays in system
verilog with example 1)copy and compare . 2) for and for each
( 3 ) ( 2 ) ( 1 ) (10)
UNIT - III L CO PO M
5 a. Explain object creation and deallocation in system verilog with an example
(4) (3) ( 1 ) (10)
b. 1)Create a class and object that contains the following members
a. An 8-bit logic data type and void function that prints the value.
b.Using the class from above, create a custom constructor, so that data is initialized to 0.
( 4 ) ( 3 ) ( 3) (5)
c. Explain 2-state data type with an example
( 3 ) ( 3 ) ( 3 ) (5)
OR
6 a. Write a short note on
1) inheritance and subclasses 2) polymorphism
( 2 ) ( 3 ) ( 1 ) (10)
b. Create a class called with a single variable that can be randomized and the variable should have
values between 2 and 6 when randomized. Also write the expected output of the class.
Note: L (Level), CO (Course Outcome), PO (Programme Outcome), M (Marks)
Advanced Digital Logic Verification
Time: 3 Hours Max. Marks: 100
Instructions: 1. Answer any one full question from each of the units.
2. Assume suitable missing data, if any.
3. Draw neat diagrams, wherever necessary
UNIT - I L CO PO M
1 a. Explain the basic testbench functionality
(2) (1) (1) (4)
b. Briefly explain functional coverage with diagrams.
(2) (1) (1) (8)
c. Interpret the different design inputs that should be randomized while generating stimulus for a
design .
(2) (1) (1) (8)
OR
2 a. Explain the different levels of testing in verification process
(2) (1) (1) (4)
b. Briefly explain directed testing with diagrams
(2) (1) (1) (8)
c. Explain typical verification flow with flow chart.
(2) (1) (1) (8)
UNIT – II L CO PO M
3 a. Write a system verilog code to illustrate different operations performed on queues.
( 4 ) ( 2 ) ( 3 ) (10)
b. Write the syntax of clocking blocks in system verilog and explain.
( 3 ) ( 2 ) ( 1 ) (10)
OR
4 a. Identify the differences between dynamic arrays and associative arrays in system verilog with
example
( 4 ) ( 2 ) ( 3 ) (10)
b. Illustrste the following operations performed on single dimensional fixed size arrays in system
verilog with example 1)copy and compare . 2) for and for each
( 3 ) ( 2 ) ( 1 ) (10)
UNIT - III L CO PO M
5 a. Explain object creation and deallocation in system verilog with an example
(4) (3) ( 1 ) (10)
b. 1)Create a class and object that contains the following members
a. An 8-bit logic data type and void function that prints the value.
b.Using the class from above, create a custom constructor, so that data is initialized to 0.
( 4 ) ( 3 ) ( 3) (5)
c. Explain 2-state data type with an example
( 3 ) ( 3 ) ( 3 ) (5)
OR
6 a. Write a short note on
1) inheritance and subclasses 2) polymorphism
( 2 ) ( 3 ) ( 1 ) (10)
b. Create a class called with a single variable that can be randomized and the variable should have
values between 2 and 6 when randomized. Also write the expected output of the class.
Note: L (Level), CO (Course Outcome), PO (Programme Outcome), M (Marks)
