IT321
Computer Systems Architecture
3.0 Credits
Midterm Exam Review (Qns & Ans)
2025
©2025
, Multiple Choice Questions
1. Question:
Which design technique divides a CPU’s instruction processing into
separate overlapping stages to improve throughput?
- a. Superscalar execution
- b. Pipelining
- c. Out‑of‑order execution
- d. Branch prediction
ANS: b. Pipelining
Rationale:
Pipelining splits instruction execution into distinct stages (fetch,
decode, execute, etc.) so that multiple instructions can be processed
concurrently, thereby increasing overall throughput.
2. Question:
Which technique allows a processor to reorder instructions
dynamically, executing them as soon as their operands are ready,
independent of the original program order?
- a. Superscalar execution
- b. Speculative execution
- c. Out‑of‑order execution
- d. Simultaneous multithreading
ANS: c. Out‑of‑order execution
Rationale:
Out‑of‑order execution improves performance by dynamically
reordering instructions to mitigate stalls, provided that the reordering
does not violate data dependencies.
3. Question:
In a multiprocessor system, which protocol is commonly implemented
to maintain consistency across the caches of multiple processors?
©2025
, - a. MSI
- b. MESI
- c. MOESI
- d. All of the above
ANS: d. All of the above
Rationale:
Various protocols—such as MSI, MESI, and MOESI—are designed to
enforce cache coherence in multiprocessor systems. Among these, MESI
is most common, but some systems may implement MOESI for additional
optimizations.
4. Question:
Which memory management concept enables a system to run
programs requiring more memory than physically available by using disk
storage?
- a. Caching
- b. Virtual memory
- c. Paging
- d. Segmentation
ANS: b. Virtual memory
Rationale:
Virtual memory abstracts physical memory through techniques like
paging and demand loading, allowing systems to run applications even
when the total memory requirement exceeds available RAM.
5. Question:
Which layer of computer architecture defines the set of instructions,
registers, and data types accessible to a programmer?
- a. Microarchitecture
- b. System architecture
- c. Instruction Set Architecture (ISA)
- d. Hardware Abstraction Layer (HAL)
©2025
, ANS: c. Instruction Set Architecture (ISA)
Rationale:
ISA is the boundary between hardware and software that defines the
supported operations, registers, addressing modes, and data types,
serving as an abstract model of the processor.
6. Question:
Which architectural feature allows a single CPU to execute multiple
threads concurrently by sharing its execution resources?
- a. Multi-core architecture
- b. Simultaneous Multithreading (SMT)
- c. Hyper-threading
- d. Both b and c
ANS: d. Both b and c
Rationale:
SMT is a technique (popularized as Hyper-threading by Intel) that
enables a single core to execute instructions from multiple threads
concurrently, thereby increasing overall utilization of CPU resources.
7. Question:
Which component in a computer system translates virtual addresses to
physical addresses?
- a. Cache controller
- b. Memory Management Unit (MMU)
- c. Bus interface unit
- d. Direct Memory Access (DMA) controller
ANS: b. Memory Management Unit (MMU)
Rationale:
The MMU uses techniques such as paging and segmentation to map
virtual addresses to physical addresses, enabling isolation and efficient
memory utilization.
8. Question:
©2025
Computer Systems Architecture
3.0 Credits
Midterm Exam Review (Qns & Ans)
2025
©2025
, Multiple Choice Questions
1. Question:
Which design technique divides a CPU’s instruction processing into
separate overlapping stages to improve throughput?
- a. Superscalar execution
- b. Pipelining
- c. Out‑of‑order execution
- d. Branch prediction
ANS: b. Pipelining
Rationale:
Pipelining splits instruction execution into distinct stages (fetch,
decode, execute, etc.) so that multiple instructions can be processed
concurrently, thereby increasing overall throughput.
2. Question:
Which technique allows a processor to reorder instructions
dynamically, executing them as soon as their operands are ready,
independent of the original program order?
- a. Superscalar execution
- b. Speculative execution
- c. Out‑of‑order execution
- d. Simultaneous multithreading
ANS: c. Out‑of‑order execution
Rationale:
Out‑of‑order execution improves performance by dynamically
reordering instructions to mitigate stalls, provided that the reordering
does not violate data dependencies.
3. Question:
In a multiprocessor system, which protocol is commonly implemented
to maintain consistency across the caches of multiple processors?
©2025
, - a. MSI
- b. MESI
- c. MOESI
- d. All of the above
ANS: d. All of the above
Rationale:
Various protocols—such as MSI, MESI, and MOESI—are designed to
enforce cache coherence in multiprocessor systems. Among these, MESI
is most common, but some systems may implement MOESI for additional
optimizations.
4. Question:
Which memory management concept enables a system to run
programs requiring more memory than physically available by using disk
storage?
- a. Caching
- b. Virtual memory
- c. Paging
- d. Segmentation
ANS: b. Virtual memory
Rationale:
Virtual memory abstracts physical memory through techniques like
paging and demand loading, allowing systems to run applications even
when the total memory requirement exceeds available RAM.
5. Question:
Which layer of computer architecture defines the set of instructions,
registers, and data types accessible to a programmer?
- a. Microarchitecture
- b. System architecture
- c. Instruction Set Architecture (ISA)
- d. Hardware Abstraction Layer (HAL)
©2025
, ANS: c. Instruction Set Architecture (ISA)
Rationale:
ISA is the boundary between hardware and software that defines the
supported operations, registers, addressing modes, and data types,
serving as an abstract model of the processor.
6. Question:
Which architectural feature allows a single CPU to execute multiple
threads concurrently by sharing its execution resources?
- a. Multi-core architecture
- b. Simultaneous Multithreading (SMT)
- c. Hyper-threading
- d. Both b and c
ANS: d. Both b and c
Rationale:
SMT is a technique (popularized as Hyper-threading by Intel) that
enables a single core to execute instructions from multiple threads
concurrently, thereby increasing overall utilization of CPU resources.
7. Question:
Which component in a computer system translates virtual addresses to
physical addresses?
- a. Cache controller
- b. Memory Management Unit (MMU)
- c. Bus interface unit
- d. Direct Memory Access (DMA) controller
ANS: b. Memory Management Unit (MMU)
Rationale:
The MMU uses techniques such as paging and segmentation to map
virtual addresses to physical addresses, enabling isolation and efficient
memory utilization.
8. Question:
©2025
