1.1.1 - Structure and function of the processor
Specification
Purpose of the CPU
● Processes data (searching,sorting,calculating,decision making and control of
input, output and storage devices)
Arithmetic Logic unit (ALU)
● Performs arithmetic and logical operations on data as well as binary shifts
● Arithmetic operations on fixed and floating point numbers
○ Addition,subtraction,multiply,divide
● Boolean logic operations
○ Comparison,AND,OR,NOT,XOR
● Uses general purpose registers to temporarily hold the results of
, calculations such as the accumulator
● Inputs from internal bus and accumulator ; Outputs routed to a register
Control Unit (CU)
● Coordinates CPU’s activities; directs flow of data/operations of the CPU
between CPU and other devices.
● Accepts the next instruction, decodes it, handles the execution and
stores the result back in registers or memory
● Sends memory read or write requests to main memory via the control bus
as well as other command and control signals e.g bus requests, bus grants,
interrupt requests etc.
● Makes extensive use of the status registers and clock
● Coordinates and communicates with all parts of the CPU
Registers
What are registers?
● They are the CPU’s own memory store. They are small memory cells that
temporarily store data. It is very quick and contains specialised registers
which are at the core of the fetch-decode-execute cycle. All
arithmetic,logical and shift operations occur in registers.
● General purpose registers available to programmers to temporarily store
data
● Dedicated/specialised registers are used by the processor to carry out a
specific role.
Name Description
Program Counter (PC) ● Holds address of next instruction to be executed
○ Next instruction in a sequence
○ Address to jump to if commanded - from CIR
● Close relationship with MAR. Contents are copied
into MAR at the start of the fetch-decode-execute
cycle. Increments by 1 after
Accumulator (ACC) ● A general-purpose register that modern CPUs
have
● Stores data or control information
● CPU has many general purpose registers to store
data temporarily while instructions or calculations
are being carried out.
● More general purpose registers in a processor =
faster it may operate
● Results of calculations done by ALU stored here
Memory Address ● Holds memory address from which data or an
instruction is to be fetched or to which data is to
Register (MAR) be written or read from
, ● Sends these addresses down the address bus
Memory Data Register ● Temporarily stores data which has been read
from or written to memory
(MDR) ● Holds instruction from MAR and associated data
● Known as the MBR (memory buffer register) - or the
gateway to the processor
● All data to and from memory passes through the
data bus and passes through the MDR
Current Instruction ● Holds the current instruction being executed
● MDR contents are copied to the CIR if it is an
Register (CIR) instruction
● Contains opcode and operand(s) of current
instruction
● Opcode = what to do e.g store, load etc.
● Operand = what do we need to do it e.g data,
address
● E.g load 1000 into ALU
○ LDA 1000
Buses
● Collection of wires/channels (that are parallel) which allow data or
instructions to be communicated between devices. They connect two or
more components together inside the CPU. These buses are collectively
called the system bus.
● The width of a bus is the number of parallel wires the bus has. The width
is directly proportional to the number of bits that can be transferred
simultaneously at any given time. E.g they are normally 8,16,32 or 64 wires
wide.
Name Description
Data bus ● Carries binary 1s and 0s that make up
actual info being transmitted.
● Responsible for moving data and
instructions between the CPU and the
main memory (and I/O devices)
● bi-directional
Address bus ● Carries memory addresses that identify
where the data is being read from or
written to (sent to or retrieved from)
● One way - from the CPU to RAM
● Width of the bus is proportional to the
number of accessible memory locations
Control bus ● Carries command and control signals
, from the control unit to and from every
other component of the CPU/computer
e.g clock signal to synchronise the
process.
● Bi-directional
● Manages data processing
● Coordinates use of the address and data
buses, provided status info between
system components.
● Control signals:
○ Bus request - device requesting use
of a data bus
○ Bus grant - CPU granted access to
data bus
○ Memory write - data written into
addressed location using this bus
○ Memory read - data read from
specific location to be placed on data
bus
Buses - how this relates to assembly language
● Computers can only deal with binary 1s and 0s but we prefer to deal in
more abstract languages we can understand
● At a low level, computers uses assembly code, a language which has a
direct one-to-one relationship with processor architecture
● E.g the assembly instruction for ‘load’ is ‘LDA’. This is known as a mnemonic
in assembly language.It is a simplified way of representing machine code.
● Assembly Code Mnemonics to know:
○ ADD: add
○ SUB: sub
○ STA: store
○ LDA: load
○ BRA: branch always
○ BRZ: branch if zero
○ BRP: branch is positive
○ INP: input
○ OUT: output
○ HLT: end program
○ DAT: data location
Specification
Purpose of the CPU
● Processes data (searching,sorting,calculating,decision making and control of
input, output and storage devices)
Arithmetic Logic unit (ALU)
● Performs arithmetic and logical operations on data as well as binary shifts
● Arithmetic operations on fixed and floating point numbers
○ Addition,subtraction,multiply,divide
● Boolean logic operations
○ Comparison,AND,OR,NOT,XOR
● Uses general purpose registers to temporarily hold the results of
, calculations such as the accumulator
● Inputs from internal bus and accumulator ; Outputs routed to a register
Control Unit (CU)
● Coordinates CPU’s activities; directs flow of data/operations of the CPU
between CPU and other devices.
● Accepts the next instruction, decodes it, handles the execution and
stores the result back in registers or memory
● Sends memory read or write requests to main memory via the control bus
as well as other command and control signals e.g bus requests, bus grants,
interrupt requests etc.
● Makes extensive use of the status registers and clock
● Coordinates and communicates with all parts of the CPU
Registers
What are registers?
● They are the CPU’s own memory store. They are small memory cells that
temporarily store data. It is very quick and contains specialised registers
which are at the core of the fetch-decode-execute cycle. All
arithmetic,logical and shift operations occur in registers.
● General purpose registers available to programmers to temporarily store
data
● Dedicated/specialised registers are used by the processor to carry out a
specific role.
Name Description
Program Counter (PC) ● Holds address of next instruction to be executed
○ Next instruction in a sequence
○ Address to jump to if commanded - from CIR
● Close relationship with MAR. Contents are copied
into MAR at the start of the fetch-decode-execute
cycle. Increments by 1 after
Accumulator (ACC) ● A general-purpose register that modern CPUs
have
● Stores data or control information
● CPU has many general purpose registers to store
data temporarily while instructions or calculations
are being carried out.
● More general purpose registers in a processor =
faster it may operate
● Results of calculations done by ALU stored here
Memory Address ● Holds memory address from which data or an
instruction is to be fetched or to which data is to
Register (MAR) be written or read from
, ● Sends these addresses down the address bus
Memory Data Register ● Temporarily stores data which has been read
from or written to memory
(MDR) ● Holds instruction from MAR and associated data
● Known as the MBR (memory buffer register) - or the
gateway to the processor
● All data to and from memory passes through the
data bus and passes through the MDR
Current Instruction ● Holds the current instruction being executed
● MDR contents are copied to the CIR if it is an
Register (CIR) instruction
● Contains opcode and operand(s) of current
instruction
● Opcode = what to do e.g store, load etc.
● Operand = what do we need to do it e.g data,
address
● E.g load 1000 into ALU
○ LDA 1000
Buses
● Collection of wires/channels (that are parallel) which allow data or
instructions to be communicated between devices. They connect two or
more components together inside the CPU. These buses are collectively
called the system bus.
● The width of a bus is the number of parallel wires the bus has. The width
is directly proportional to the number of bits that can be transferred
simultaneously at any given time. E.g they are normally 8,16,32 or 64 wires
wide.
Name Description
Data bus ● Carries binary 1s and 0s that make up
actual info being transmitted.
● Responsible for moving data and
instructions between the CPU and the
main memory (and I/O devices)
● bi-directional
Address bus ● Carries memory addresses that identify
where the data is being read from or
written to (sent to or retrieved from)
● One way - from the CPU to RAM
● Width of the bus is proportional to the
number of accessible memory locations
Control bus ● Carries command and control signals
, from the control unit to and from every
other component of the CPU/computer
e.g clock signal to synchronise the
process.
● Bi-directional
● Manages data processing
● Coordinates use of the address and data
buses, provided status info between
system components.
● Control signals:
○ Bus request - device requesting use
of a data bus
○ Bus grant - CPU granted access to
data bus
○ Memory write - data written into
addressed location using this bus
○ Memory read - data read from
specific location to be placed on data
bus
Buses - how this relates to assembly language
● Computers can only deal with binary 1s and 0s but we prefer to deal in
more abstract languages we can understand
● At a low level, computers uses assembly code, a language which has a
direct one-to-one relationship with processor architecture
● E.g the assembly instruction for ‘load’ is ‘LDA’. This is known as a mnemonic
in assembly language.It is a simplified way of representing machine code.
● Assembly Code Mnemonics to know:
○ ADD: add
○ SUB: sub
○ STA: store
○ LDA: load
○ BRA: branch always
○ BRZ: branch if zero
○ BRP: branch is positive
○ INP: input
○ OUT: output
○ HLT: end program
○ DAT: data location
