PRACTICAL EXPERIMENT 1.
IMPLEMENTATION AND ANALYSIS OF A LATCH AND J-K FLIP-FLOP CIRCUIT
1.1. OBJECTIVE:
1. Construct a latch using NAND gates to supply a single pulse
when triggered via a switch at the input. This pulse can be
used as a clock pulse for a gate circuit, shift register or
counter circuits. The advantage of using this latch is that
it eliminates contact bounce.
2. Use the SDPT switch on the Latch to supply a J-K Flip-Flop
with clock pulse.
3. Illustrate the operation of the JK Flip-Flip by means of a
practical circuit.
1.2. COMPONENTS:
1 x IC 74LS00N (quad 2-input open-collector NAND gate)
4 x LED 5 mm LEDs
1 x IC 74HCT112 Dual JK negative edge triggered
Flip-Flop with pre-set.
SDPT switch
x 3 ¼ Watt metal film through hole resistors
Resistors
1.3. EQUIPMENT: Development board
Logic Probe
Digital Multi-meter
Connecting wires
5V power supply
PROCEDURE
Contract the circuit as show above and use the latch to be the input
clock pulse of the J-K flip-flop .Use the switches to be the input of
the j-k flip-flop and record the output Q and Q bar.
Compare the Multisim results and constructed results and record the
information. Check the operation of the latch before using it as the
clock to the J-k Flip-Flop.
Make sure the J-K flip flop used has a negative triggering pulse.
DIGITAL SYSTEMS II PAGE 2 PRACTICAL REPORT
, 1.4 CIRCUIT DIAGRAM:
E
: xperiment 1 Latch and J -K Flip Flop Circuit diagram
Simulation circuit diagram
DIGITAL SYSTEMS II PAGE 3 PRACTICAL REPORT
IMPLEMENTATION AND ANALYSIS OF A LATCH AND J-K FLIP-FLOP CIRCUIT
1.1. OBJECTIVE:
1. Construct a latch using NAND gates to supply a single pulse
when triggered via a switch at the input. This pulse can be
used as a clock pulse for a gate circuit, shift register or
counter circuits. The advantage of using this latch is that
it eliminates contact bounce.
2. Use the SDPT switch on the Latch to supply a J-K Flip-Flop
with clock pulse.
3. Illustrate the operation of the JK Flip-Flip by means of a
practical circuit.
1.2. COMPONENTS:
1 x IC 74LS00N (quad 2-input open-collector NAND gate)
4 x LED 5 mm LEDs
1 x IC 74HCT112 Dual JK negative edge triggered
Flip-Flop with pre-set.
SDPT switch
x 3 ¼ Watt metal film through hole resistors
Resistors
1.3. EQUIPMENT: Development board
Logic Probe
Digital Multi-meter
Connecting wires
5V power supply
PROCEDURE
Contract the circuit as show above and use the latch to be the input
clock pulse of the J-K flip-flop .Use the switches to be the input of
the j-k flip-flop and record the output Q and Q bar.
Compare the Multisim results and constructed results and record the
information. Check the operation of the latch before using it as the
clock to the J-k Flip-Flop.
Make sure the J-K flip flop used has a negative triggering pulse.
DIGITAL SYSTEMS II PAGE 2 PRACTICAL REPORT
, 1.4 CIRCUIT DIAGRAM:
E
: xperiment 1 Latch and J -K Flip Flop Circuit diagram
Simulation circuit diagram
DIGITAL SYSTEMS II PAGE 3 PRACTICAL REPORT
