Quinten Maas
SAMENVATTING HARDWARE
P1
INHOUD
Talstelsels ................................................................................................................................................................ 2
Negatieve getallen .................................................................................................................................................. 4
Binair in informatica ................................................................................................................................................ 5
Karaktersets ............................................................................................................................................................ 6
Rekenen met binaire getallen ................................................................................................................................. 7
Kommagetallen ....................................................................................................................................................... 9
Logische schakelingen ........................................................................................................................................... 11
Wetten van De Morgan ..................................................................................................................................... 13
Andere eigenschappen...................................................................................................................................... 13
Karnaugh kaarten .............................................................................................................................................. 14
Veel voorkomende logische schakelingen ............................................................................................................ 16
mux.................................................................................................................................................................... 16
DEMUX .............................................................................................................................................................. 17
Half adder .......................................................................................................................................................... 17
Full adder .......................................................................................................................................................... 18
vergelijker (comparator) ................................................................................................................................... 19
Hoofdstuk 6: Sequentiële schakelingen ................................................................................................................ 20
RS latch: ............................................................................................................................................................. 20
schema .......................................................................................................................................................... 20
tijdsdiagram .................................................................................................................................................. 20
Syndrone RS-latch : ........................................................................................................................................... 21
schema .......................................................................................................................................................... 21
Tijdsdiagram .................................................................................................................................................. 21
Syndrone D-latch ............................................................................................................................................... 22
schema .......................................................................................................................................................... 22
Tijdsdiagram .................................................................................................................................................. 22
symbool ......................................................................................................................................................... 22
master-slave D flip-flop ..................................................................................................................................... 23
schema .......................................................................................................................................................... 23
Tijdsdiagram .................................................................................................................................................. 23
symbool ......................................................................................................................................................... 23
1
,Quinten Maas
T flip flop: .......................................................................................................................................................... 24
schema .......................................................................................................................................................... 24
Tijdsdiagram .................................................................................................................................................. 24
Hoodstuk 7: Veel voorkomende sequentiële schakelingen .................................................................................. 24
tellers ................................................................................................................................................................ 24
Tijdsdiagram .................................................................................................................................................. 25
Registers ............................................................................................................................................................ 25
shift-registers .................................................................................................................................................... 25
tijdsdiagram .................................................................................................................................................. 25
Hoofdstuk 8: tri-state buffers................................................................................................................................ 26
Principe ............................................................................................................................................................. 26
SRAM geheugen ................................................................................................................................................ 27
De processor ......................................................................................................................................................... 28
Opbouw ............................................................................................................................................................. 28
Instructieset ...................................................................................................................................................... 28
De compiler ....................................................................................................................................................... 30
TALSTELSELS
Decimaal (base 10)
0-9
Java:
Binair (base 2)
0-1
Java: 0b
Hexadecimaal (base 16)
0-F
Java: 0x
Octaal (base 8)
0-8
Java: 0
2
, Quinten Maas
Veranderen van talstelsels
Base G => 10
[]10 =∑𝑎𝑖*Gi
Voorbeeld: (G = 5)
[123]5 = 1*52 + 2*51 + 3*50 = [38]10
Base 10 => G
Deelmethode
Voorbeeld: [1234]10 => []16
3
SAMENVATTING HARDWARE
P1
INHOUD
Talstelsels ................................................................................................................................................................ 2
Negatieve getallen .................................................................................................................................................. 4
Binair in informatica ................................................................................................................................................ 5
Karaktersets ............................................................................................................................................................ 6
Rekenen met binaire getallen ................................................................................................................................. 7
Kommagetallen ....................................................................................................................................................... 9
Logische schakelingen ........................................................................................................................................... 11
Wetten van De Morgan ..................................................................................................................................... 13
Andere eigenschappen...................................................................................................................................... 13
Karnaugh kaarten .............................................................................................................................................. 14
Veel voorkomende logische schakelingen ............................................................................................................ 16
mux.................................................................................................................................................................... 16
DEMUX .............................................................................................................................................................. 17
Half adder .......................................................................................................................................................... 17
Full adder .......................................................................................................................................................... 18
vergelijker (comparator) ................................................................................................................................... 19
Hoofdstuk 6: Sequentiële schakelingen ................................................................................................................ 20
RS latch: ............................................................................................................................................................. 20
schema .......................................................................................................................................................... 20
tijdsdiagram .................................................................................................................................................. 20
Syndrone RS-latch : ........................................................................................................................................... 21
schema .......................................................................................................................................................... 21
Tijdsdiagram .................................................................................................................................................. 21
Syndrone D-latch ............................................................................................................................................... 22
schema .......................................................................................................................................................... 22
Tijdsdiagram .................................................................................................................................................. 22
symbool ......................................................................................................................................................... 22
master-slave D flip-flop ..................................................................................................................................... 23
schema .......................................................................................................................................................... 23
Tijdsdiagram .................................................................................................................................................. 23
symbool ......................................................................................................................................................... 23
1
,Quinten Maas
T flip flop: .......................................................................................................................................................... 24
schema .......................................................................................................................................................... 24
Tijdsdiagram .................................................................................................................................................. 24
Hoodstuk 7: Veel voorkomende sequentiële schakelingen .................................................................................. 24
tellers ................................................................................................................................................................ 24
Tijdsdiagram .................................................................................................................................................. 25
Registers ............................................................................................................................................................ 25
shift-registers .................................................................................................................................................... 25
tijdsdiagram .................................................................................................................................................. 25
Hoofdstuk 8: tri-state buffers................................................................................................................................ 26
Principe ............................................................................................................................................................. 26
SRAM geheugen ................................................................................................................................................ 27
De processor ......................................................................................................................................................... 28
Opbouw ............................................................................................................................................................. 28
Instructieset ...................................................................................................................................................... 28
De compiler ....................................................................................................................................................... 30
TALSTELSELS
Decimaal (base 10)
0-9
Java:
Binair (base 2)
0-1
Java: 0b
Hexadecimaal (base 16)
0-F
Java: 0x
Octaal (base 8)
0-8
Java: 0
2
, Quinten Maas
Veranderen van talstelsels
Base G => 10
[]10 =∑𝑎𝑖*Gi
Voorbeeld: (G = 5)
[123]5 = 1*52 + 2*51 + 3*50 = [38]10
Base 10 => G
Deelmethode
Voorbeeld: [1234]10 => []16
3
