Difference between UP counter and DOWN counter
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Same polarity = DOWN counters
Datasheet
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A printed specification giving details of the pin configuration, electrical
properties, and mechanical profile of an electronic device.
Karnaugh Map (KMAP)
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A graphical tool for finding the maximum SOP or POS simplification of a
Boolean expression. A Karnaugh map works by arranging the terms of an
expression so that variable scans are cancelled by grouping minterms or
maxterms.
Adjacent Cell
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Two cells in a K-map are adjacent if there is only one variable that is
different between the coordinates of the two cells.
Target Device
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The specific PLD for which a digital design is intended.
When comparing a PLD circuit to a logic circuit implemented with individual logic
gates, the PLD circuit will ____________.
1. be easier to breadboard with
fewer chips and wires.
2. require more chips and wiring.
3. require you to simplify the
expression using a K-Map.
,4.require a higher operating voltage.
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be easier to breadboard with
fewer chips and wires.
74LS08
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AND Gate.
Compiler
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The process used by CPLD design software to interpret design information
(such as a schematic or text file) and create required programming
information for a CPLD.
. Which of the following is the simplified equivalent for the Boolean equation shown?
F = Y' +XY'
1. F = X ''Y''
2. F = X
3. F = X Y'
4. F = Y'
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, F = Y'
INVERTER gate (NOT)
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Also called an inverting buffer. A logic gate that changes its input logic
level to the opposite state.
74LS02
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NOR Gate.
AND Gate
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Digital circuit that implements the AND operation. The output of this circuit
is HIGH only if all of its inputs are HIGH.
Amplitude
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Same polarity = DOWN counters
Datasheet
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A printed specification giving details of the pin configuration, electrical
properties, and mechanical profile of an electronic device.
Karnaugh Map (KMAP)
,Give this one a try later!
A graphical tool for finding the maximum SOP or POS simplification of a
Boolean expression. A Karnaugh map works by arranging the terms of an
expression so that variable scans are cancelled by grouping minterms or
maxterms.
Adjacent Cell
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Two cells in a K-map are adjacent if there is only one variable that is
different between the coordinates of the two cells.
Target Device
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The specific PLD for which a digital design is intended.
When comparing a PLD circuit to a logic circuit implemented with individual logic
gates, the PLD circuit will ____________.
1. be easier to breadboard with
fewer chips and wires.
2. require more chips and wiring.
3. require you to simplify the
expression using a K-Map.
,4.require a higher operating voltage.
Give this one a try later!
be easier to breadboard with
fewer chips and wires.
74LS08
Give this one a try later!
AND Gate.
Compiler
Give this one a try later!
The process used by CPLD design software to interpret design information
(such as a schematic or text file) and create required programming
information for a CPLD.
. Which of the following is the simplified equivalent for the Boolean equation shown?
F = Y' +XY'
1. F = X ''Y''
2. F = X
3. F = X Y'
4. F = Y'
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, F = Y'
INVERTER gate (NOT)
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Also called an inverting buffer. A logic gate that changes its input logic
level to the opposite state.
74LS02
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NOR Gate.
AND Gate
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Digital circuit that implements the AND operation. The output of this circuit
is HIGH only if all of its inputs are HIGH.
Amplitude
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