ECEN 454: Final Exam Review
questions n answers rated A+
What is the ordering of layers in CMOS fabrication? - ANS ✔Body, Diffusion, Thin Oxide
Where does the depletion layer form? - ANS ✔Surrounding the diffusion region
When does nMOS operate in saturation mode? - ANS ✔Vgs > Vt
The diffusion capacitance of a drain node is proportional to what? - ANS ✔Transistor Width
What is an incorrect reason for non-ideal transistor behavior? - ANS ✔Pinch off in saturation
The channel length modulation coefficient: - ANS ✔Increases or decreases ids linearly with Vds
Threshold Voltage: - ANS ✔depends on body effect
What is true about degraded mobility of nMOS transistors in real devices? - ANS ✔It is
geometrically related to Vgs
nMOS pass transistors pull no higher than ___________ - ANS ✔Vdd - Vtn
pMOS pass transistors pull no lower than ____________ - ANS ✔Vtp
nMOS Cutoff - ANS ✔Vin < Vtn
, nMOS Linear - ANS ✔Vin > Vtn, Vout < Vin - Vtn
nMOS Saturated - ANS ✔Vin > Vtn, Vout > Vin - Vtn
pMOS Cutoff - ANS ✔Vin > Vdd + Vtp
pMOS Linear - ANS ✔Vin < Vdd + Vtp, Vout > Vin - Vtp
pMOS Saturated - ANS ✔Vin < Vdd + Vtp, Vout < Vin - Vtp
DC analysis tells us Vout if ___________ is constant - ANS ✔Vin
Transient Analysis tells us Vout(t) if ___________ changes - ANS ✔Vin(t)
___________ is a method that helps find the best circuit topology for a function, the number of
stages of logic that give the least delay, and how wide transistors should be. - ANS ✔Logical
Effort
Transistors are built on a __________. - ANS ✔Silicon Substrate
Silicon is a __________. - ANS ✔Semiconductor
Pure silicon has no free carriers and conducts ___________ - ANS ✔Poorly
Adding dopants increases the ___________ - ANS ✔Conductivity
questions n answers rated A+
What is the ordering of layers in CMOS fabrication? - ANS ✔Body, Diffusion, Thin Oxide
Where does the depletion layer form? - ANS ✔Surrounding the diffusion region
When does nMOS operate in saturation mode? - ANS ✔Vgs > Vt
The diffusion capacitance of a drain node is proportional to what? - ANS ✔Transistor Width
What is an incorrect reason for non-ideal transistor behavior? - ANS ✔Pinch off in saturation
The channel length modulation coefficient: - ANS ✔Increases or decreases ids linearly with Vds
Threshold Voltage: - ANS ✔depends on body effect
What is true about degraded mobility of nMOS transistors in real devices? - ANS ✔It is
geometrically related to Vgs
nMOS pass transistors pull no higher than ___________ - ANS ✔Vdd - Vtn
pMOS pass transistors pull no lower than ____________ - ANS ✔Vtp
nMOS Cutoff - ANS ✔Vin < Vtn
, nMOS Linear - ANS ✔Vin > Vtn, Vout < Vin - Vtn
nMOS Saturated - ANS ✔Vin > Vtn, Vout > Vin - Vtn
pMOS Cutoff - ANS ✔Vin > Vdd + Vtp
pMOS Linear - ANS ✔Vin < Vdd + Vtp, Vout > Vin - Vtp
pMOS Saturated - ANS ✔Vin < Vdd + Vtp, Vout < Vin - Vtp
DC analysis tells us Vout if ___________ is constant - ANS ✔Vin
Transient Analysis tells us Vout(t) if ___________ changes - ANS ✔Vin(t)
___________ is a method that helps find the best circuit topology for a function, the number of
stages of logic that give the least delay, and how wide transistors should be. - ANS ✔Logical
Effort
Transistors are built on a __________. - ANS ✔Silicon Substrate
Silicon is a __________. - ANS ✔Semiconductor
Pure silicon has no free carriers and conducts ___________ - ANS ✔Poorly
Adding dopants increases the ___________ - ANS ✔Conductivity
