CEA201 FULL EXAM PACK |EXAM BANK QUESTIONS AND ANSWERS| LATEST
UPDATE
__________ are a set of storage locations.
A. Processors
B. PSWs
C. Registers
D. Control units - ✔ANSWER Registers
The ________ controls the movement of data and instructions into and out of the processor.
A. control unit
B. ALU
C. shifter
D. branch - ✔ANSWER control unit
________ registers may be used only to hold data and cannot be employed in the calculation of
an operand address.
A. General purpose
B. Data
C. Address
D. Condition code - ✔ANSWER Data
__________ are bits set by the processor hardware as the result of operations.
A. MIPS
B. Condition codes
C. Stacks
D. PSWs - ✔ANSWER Condition codes
,The _________ contains the address of an instruction to be fetched.
A. instruction register
B. memory address register
C. memory buffer register
D. program counter - ✔ANSWER program counter
The _________ contains a word of data to be written to memory or the word most recently
read.
A. MAR
B. PC
C. MBR
D. IR - ✔ANSWER MBR
The ________ determines the opcode and the operand specifiers.
A. decode instruction
B. fetch operands
C. calculate operands
D. execute instruction - ✔ANSWER decode instruction
_________ is a pipeline hazard.
A. Control
B. Resource
C. Data
D. All of the above - ✔ANSWER All of the above
A ________ hazard occurs when there is a conflict in the access of an operand location.
,A. resource
B. data
C. structural
D. control - ✔ANSWER data
A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of
the pipeline and containing the n most recently fetched instructions in sequence.
A. loop buffer
B. delayed branch
C. multiple stream
D. branch prediction - ✔ANSWER loop buffer
The _________ is a small cache memory associated with the instruction fetch stage of the
pipeline.
A. dynamic branch
B. loop table
C. branch history table
D. flag - ✔ANSWER branch history table
The _________ stage includes ALU operations, cache access, and register update.
A. decode
B. execute
C. fetch
D. write back - ✔ANSWER execute
________ is used for debugging.
A. Direction flag
B. Alignment check
, C. Trap flag
D. Identification flag - ✔ANSWER Trap flag
The ARM architecture supports _______ execution modes.
A. 2
B. 8
C. 11
D. 7 - ✔ANSWER 7
The OS usually runs in ________.
A. supervisor mode
B. abort mode
C. undefined mode
D. fast interrupt mode - ✔ANSWER supervisor mode
rapid - ✔ANSWER Computer technology is changing at a __________ pace.
a. slow
b. slow to medium
c. rapid
d. non-existent
architecture - ✔ANSWER Computer _________ refers to those attributes that have a direct
impact on the logical execution of a program.
a. organization
b. specifics
c. design
UPDATE
__________ are a set of storage locations.
A. Processors
B. PSWs
C. Registers
D. Control units - ✔ANSWER Registers
The ________ controls the movement of data and instructions into and out of the processor.
A. control unit
B. ALU
C. shifter
D. branch - ✔ANSWER control unit
________ registers may be used only to hold data and cannot be employed in the calculation of
an operand address.
A. General purpose
B. Data
C. Address
D. Condition code - ✔ANSWER Data
__________ are bits set by the processor hardware as the result of operations.
A. MIPS
B. Condition codes
C. Stacks
D. PSWs - ✔ANSWER Condition codes
,The _________ contains the address of an instruction to be fetched.
A. instruction register
B. memory address register
C. memory buffer register
D. program counter - ✔ANSWER program counter
The _________ contains a word of data to be written to memory or the word most recently
read.
A. MAR
B. PC
C. MBR
D. IR - ✔ANSWER MBR
The ________ determines the opcode and the operand specifiers.
A. decode instruction
B. fetch operands
C. calculate operands
D. execute instruction - ✔ANSWER decode instruction
_________ is a pipeline hazard.
A. Control
B. Resource
C. Data
D. All of the above - ✔ANSWER All of the above
A ________ hazard occurs when there is a conflict in the access of an operand location.
,A. resource
B. data
C. structural
D. control - ✔ANSWER data
A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of
the pipeline and containing the n most recently fetched instructions in sequence.
A. loop buffer
B. delayed branch
C. multiple stream
D. branch prediction - ✔ANSWER loop buffer
The _________ is a small cache memory associated with the instruction fetch stage of the
pipeline.
A. dynamic branch
B. loop table
C. branch history table
D. flag - ✔ANSWER branch history table
The _________ stage includes ALU operations, cache access, and register update.
A. decode
B. execute
C. fetch
D. write back - ✔ANSWER execute
________ is used for debugging.
A. Direction flag
B. Alignment check
, C. Trap flag
D. Identification flag - ✔ANSWER Trap flag
The ARM architecture supports _______ execution modes.
A. 2
B. 8
C. 11
D. 7 - ✔ANSWER 7
The OS usually runs in ________.
A. supervisor mode
B. abort mode
C. undefined mode
D. fast interrupt mode - ✔ANSWER supervisor mode
rapid - ✔ANSWER Computer technology is changing at a __________ pace.
a. slow
b. slow to medium
c. rapid
d. non-existent
architecture - ✔ANSWER Computer _________ refers to those attributes that have a direct
impact on the logical execution of a program.
a. organization
b. specifics
c. design
