Build larger Mux wh
I bit MUX- uses set
of select Lines Implement Logic 8 : 1 Max
equality to choose to connect
input path
-
an
=) of the output
F= Exyz)1 3 5 7) , ,
,
Place i In inputs
Do a-
b - 0 variable entered truth table
selected
G0 elsewhere
by minterm
In
S
, So 13 I In To
b ab a a o
a O So
Evxyz (3
⑳ - F =
v X yz
,
4 6, 7, 8, 9 10
,
F
, ,
13)
·
·
Xnor
0-Io
!
So
Condense by checking for a = back
Complete logic family -
- -
b O
And
verification
: E
manual Slots ·
determine
draw truth tablewt specs then map
a
design meets desired specs .
rows
S
9B ~
Y
through design logic & tabulate B
of design for
:
Verify the two are the same
inverter
Extend #
of inputs can use a
AOB
to "select" which Max
output pins put wil
↓
Specs :
F :
Exyz(0 ,
1 6
, ,
7) in hand
gates to
processor input Then . read the
process input .
heal
41/0 pins to read 8 inputs
= A + 13 you can use
suffers from speed
:
>
A
-
F= Y + XY
Espec =
Edesigned
2 Enc
↳ Fansigneda Logic Half adder
: Mult. by powe
" ! full adder
NODan S
Half
d
adder
X F10
0001
G
Sum
xi -
O
G Cirl
# FOX i +
1000 2
1
OI
19
I I I
! + 27x2
Cont Sum
Cour Sum > Il100
Value
Fixing-selecting output to be either /F
11
gives
#
ofzeros t
means to
force the value
of a wire or input to
B A
Cir
Full adder :
A A
one
of four states : an OI
half adder X 16 x 10000
af of Ef = 0 Cout S
B A () Bits 000
v-f =
1 of = 1
half adder Cin () Sum
<
>
Ax2"
A0000
Cout S Sum
=)) -
o
]) -
a B A
=)
half adder
↑ =D -
a i =) -
1
Cout S Cout
=) () carry shift left
-
mult
shift right-division
Enable Funct idea to select blu =)
is ↳ no
fractions
-
.
a
Signal & 0 The enable
a .
signal in
of achieves this.
RippleCaryAdder-addbinwycascadingmultiple fulladdrext
combo a
gate Mak
Active Low
active
High
F = a + en ↳sig
Daen ↑ 7) -
Cale
of sum must wait
for
the
carry signal
to
propagate through all
stages
close to: close to : before the final result is available
if en = 1 then f = a
if enable = 0 then F = a
-
slow adder but basic structure
else F = /
else f0 =
Az B2
20
Bo to
& B A,
selects blu a selects blu a B2 Az , A B
A A S2- S C
Combine Enable & Value
Fixing Y2 adder Y2 adder Y2 adder
gen Pro
Cout Cin) Cout Cinc Cout Win
11
·
X= 0 S
S
S
X(select) I g2 P2
Dol
X= 1
s
Cout Max path length
Si
cascadeCog
G
cout3
Fax additive nature
Encoders -
accept 1 of
comes
from
several inputs & Prop -
i
do
generate a
binary that represents that input
lactive high)
=>
then F
if X 1 a
= =
else F = b OnEfIntIt A
01 =
17 + In + 1z + 12 gen
I bit MUX- uses set
of select Lines Implement Logic 8 : 1 Max
equality to choose to connect
input path
-
an
=) of the output
F= Exyz)1 3 5 7) , ,
,
Place i In inputs
Do a-
b - 0 variable entered truth table
selected
G0 elsewhere
by minterm
In
S
, So 13 I In To
b ab a a o
a O So
Evxyz (3
⑳ - F =
v X yz
,
4 6, 7, 8, 9 10
,
F
, ,
13)
·
·
Xnor
0-Io
!
So
Condense by checking for a = back
Complete logic family -
- -
b O
And
verification
: E
manual Slots ·
determine
draw truth tablewt specs then map
a
design meets desired specs .
rows
S
9B ~
Y
through design logic & tabulate B
of design for
:
Verify the two are the same
inverter
Extend #
of inputs can use a
AOB
to "select" which Max
output pins put wil
↓
Specs :
F :
Exyz(0 ,
1 6
, ,
7) in hand
gates to
processor input Then . read the
process input .
heal
41/0 pins to read 8 inputs
= A + 13 you can use
suffers from speed
:
>
A
-
F= Y + XY
Espec =
Edesigned
2 Enc
↳ Fansigneda Logic Half adder
: Mult. by powe
" ! full adder
NODan S
Half
d
adder
X F10
0001
G
Sum
xi -
O
G Cirl
# FOX i +
1000 2
1
OI
19
I I I
! + 27x2
Cont Sum
Cour Sum > Il100
Value
Fixing-selecting output to be either /F
11
gives
#
ofzeros t
means to
force the value
of a wire or input to
B A
Cir
Full adder :
A A
one
of four states : an OI
half adder X 16 x 10000
af of Ef = 0 Cout S
B A () Bits 000
v-f =
1 of = 1
half adder Cin () Sum
<
>
Ax2"
A0000
Cout S Sum
=)) -
o
]) -
a B A
=)
half adder
↑ =D -
a i =) -
1
Cout S Cout
=) () carry shift left
-
mult
shift right-division
Enable Funct idea to select blu =)
is ↳ no
fractions
-
.
a
Signal & 0 The enable
a .
signal in
of achieves this.
RippleCaryAdder-addbinwycascadingmultiple fulladdrext
combo a
gate Mak
Active Low
active
High
F = a + en ↳sig
Daen ↑ 7) -
Cale
of sum must wait
for
the
carry signal
to
propagate through all
stages
close to: close to : before the final result is available
if en = 1 then f = a
if enable = 0 then F = a
-
slow adder but basic structure
else F = /
else f0 =
Az B2
20
Bo to
& B A,
selects blu a selects blu a B2 Az , A B
A A S2- S C
Combine Enable & Value
Fixing Y2 adder Y2 adder Y2 adder
gen Pro
Cout Cin) Cout Cinc Cout Win
11
·
X= 0 S
S
S
X(select) I g2 P2
Dol
X= 1
s
Cout Max path length
Si
cascadeCog
G
cout3
Fax additive nature
Encoders -
accept 1 of
comes
from
several inputs & Prop -
i
do
generate a
binary that represents that input
lactive high)
=>
then F
if X 1 a
= =
else F = b OnEfIntIt A
01 =
17 + In + 1z + 12 gen
