1/28/25, 8:25 AM WGU C952
WGU C952-PA and OA| Explore New 237 Actual
Questions and Answers|2025 Update 100% Correct
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WGU C952
237 Correct terms
Questions and answers
,1/28/25, 8:25 AM WGU C952
1 of 237
Definition
the 4-bit ALU control input using a small control unit that has as
inputs the opcode field of the instruction and a 2-bit control field
indicates whether the operation to be performed should be add
(00) for loads and stores, pass input b (01) for CBZ, or be determined
by the operation encoded in the opcode field (10)
10 is ORR, AND, SUB, ADD (R-type)
00 is LDUR, STUR
01 is CBZ
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Alusrc ALUOp
Zero Armv7
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2 of 237
Definition
A multiprocessor in which latency to any word in main memory is
about the same no matter which processor requests the access.
,1/28/25, 8:25 AM WGU C952
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Uniform Memory Access
Locking Memory Access (lma)
(UMA)
Data Memory Access (mem) Flash memory
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3 of 237
Definition
Move instruction from memory to the control unit
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Application binary interface (ABI) Memory Hierarchy
memory ready signal Instruction Fetch (IF)
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4 of 237
Definition
A commit in which the results of pipelined execution are written to
the programmer-visible state in the same order that instructions are
fetched.
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next-state machine sequenced commit
in-order commit commit unit
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Term
Load-use data hazard:
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A specific form of data hazard in which the data being loaded by a load
instruction has not yet become available when it is needed by another
instruction.
WGU C952-PA and OA| Explore New 237 Actual
Questions and Answers|2025 Update 100% Correct
Correct
Incorrect
WGU C952
237 Correct terms
Questions and answers
,1/28/25, 8:25 AM WGU C952
1 of 237
Definition
the 4-bit ALU control input using a small control unit that has as
inputs the opcode field of the instruction and a 2-bit control field
indicates whether the operation to be performed should be add
(00) for loads and stores, pass input b (01) for CBZ, or be determined
by the operation encoded in the opcode field (10)
10 is ORR, AND, SUB, ADD (R-type)
00 is LDUR, STUR
01 is CBZ
Give this one a go later!
Alusrc ALUOp
Zero Armv7
Don't know?
2 of 237
Definition
A multiprocessor in which latency to any word in main memory is
about the same no matter which processor requests the access.
,1/28/25, 8:25 AM WGU C952
Give this one a go later!
Uniform Memory Access
Locking Memory Access (lma)
(UMA)
Data Memory Access (mem) Flash memory
Don't know?
3 of 237
Definition
Move instruction from memory to the control unit
Give this one a go later!
Application binary interface (ABI) Memory Hierarchy
memory ready signal Instruction Fetch (IF)
Don't know?
, 1/28/25, 8:25 AM WGU C952
4 of 237
Definition
A commit in which the results of pipelined execution are written to
the programmer-visible state in the same order that instructions are
fetched.
Give this one a go later!
next-state machine sequenced commit
in-order commit commit unit
Don't know?
5 of 237
Term
Load-use data hazard:
Give this one a go later!
A specific form of data hazard in which the data being loaded by a load
instruction has not yet become available when it is needed by another
instruction.
