CEA201 ACTUAL EXAM QUESTIONS
AND CORRECT ANSWERS (VERIFIED
ANSWERS) ALREADY GRADED A+
Q1: _________ determines the control and pipeline organization.
5/5
A. Calculation
B. Execution sequencing
C. Operations performed
D. Operands used - Answer-B. Execution sequencing
Q2: The Patterson study examined the dynamic behavior of _________ programs,
independent of the underlying architecture. *
5/5
A. HLL
B. RISC
C. CISC
D. all of the above - Answer-A. HLL
Q3: _________ is the fastest available storage device.
5/5
A. Main memory
B. Cache
C. Register storage
D. HLL - Answer-C. Register storage
Q4: The first commercial RISC product was _________.
5/5
A. SPARC
B. CISC
C. VAX
D. the Pyramid - Answer-D. the Pyramid
Q5: _________ instructions are used to position quantities in registers temporarily for
computational operations.
5/5
,A. Load-and-store
B. Window
C. Complex
D. Branch - Answer-A. Load-and-store
Q6: Which stage is required for load and store operations?
5/5
A. I
B. E
C. D
D. all of the above - Answer-D. all of the above
Q7: A ________ instruction can be used to account for data and branch delays. *
5/5
A. SUB
B. NOOP
C. JUMP
D. all of the above - Answer-B. NOOP
Q8: The instruction location immediately following the delayed branch is referred to as
the ________.
5/5
A. delay load
B. delay file
C. delay slot
D. delay register - Answer-C. delay slot
Q9: The _________ stage includes ALU operations, cache access, and register update.
5/5
A. decode
B. execute
C. fetch
D. write back - Answer-B. execute
Q10: The MIPS R4000 uses ________ bits for all internal and external data paths and
for addresses, registers, and the ALU.
5/5
A. 16
B. 32
C. 64
D. 128 - Answer-C. 64
Q11: All MIPS R series processor instructions are encoded in a single ________ word
format.
5/5
A. 4-bit
,B. 8-bit
C. 16-bit
D. 32-bit - Answer-D. 32-bit
Q12: A _________ architecture is one that makes use of more, and more fine-grained
pipeline stages.
5/5
A. parallel
B. superpipelined
C. superscalar
D. hybrid - Answer-B. superpipelined
Q13: The R4000 can have as many as _______ instructions in the pipeline at the same
time.
5/5
A. 8
B. 10
C. 5
D. 3 - Answer-A. 8
Q14: The R4000 pipeline stage where the instruction result is written back to the
register file is the __________ stage.
5/5
A. write back
B. tag check
C. data cache
D. instruction execute - Answer-A. write back
Q15: SPARC refers to an architecture defined by ________.
5/5
A. Microsoft
B. Apple
C. Sun Microsystems
D. IBM - Answer-C. Sun Microsystems
Q16: The _________ contains a word of data to be written to memory or the word most
recently read
5/5
A. MAR
B. PC
C. MBR
D. IR - Answer-C. MBR
Q17: The ________ determines the opcode and the operand specifiers.
5/5
A. decode instruction
, B. fetch operands
C. calculate operands
D. execute instruction - Answer-A. decode instruction
Q18: A ________ hazard occurs when there is a conflict in the access of an operand
location.
5/5
A. resource
B. data
C. structural
D. control - Answer-B. data
Q20: The _________ is a small cache memory associated with the instruction fetch
stage of the pipeline.
5/5
A. dynamic branch
B. loop table
C. branch history table
D. flag - Answer-C. branch history table
Q1: The superscalar approach can be used on __________ architecture.
5/5
A. RISC
B. CISC
C. neither RISC nor CISC
D. both RISC and CISC - Answer-D. both RISC and CISC
Q2: The essence of the ________ approach is the ability to execute instructions
independently and concurrently in different pipelines.
5/5
A. scalar
B. branch
C. superscalar
D. flow dependency - Answer-C. superscalar
Q3: Which of the following is a fundamental limitation to parallelism with which the
system must cope?
5/5
A. procedural dependency
B. resource conflicts
C. antidependency
D. all of the above - Answer-D. all of the above
Q4: The situation where the second instruction needs data produced by the first
instruction to execute is referred to as __________.
5/5
AND CORRECT ANSWERS (VERIFIED
ANSWERS) ALREADY GRADED A+
Q1: _________ determines the control and pipeline organization.
5/5
A. Calculation
B. Execution sequencing
C. Operations performed
D. Operands used - Answer-B. Execution sequencing
Q2: The Patterson study examined the dynamic behavior of _________ programs,
independent of the underlying architecture. *
5/5
A. HLL
B. RISC
C. CISC
D. all of the above - Answer-A. HLL
Q3: _________ is the fastest available storage device.
5/5
A. Main memory
B. Cache
C. Register storage
D. HLL - Answer-C. Register storage
Q4: The first commercial RISC product was _________.
5/5
A. SPARC
B. CISC
C. VAX
D. the Pyramid - Answer-D. the Pyramid
Q5: _________ instructions are used to position quantities in registers temporarily for
computational operations.
5/5
,A. Load-and-store
B. Window
C. Complex
D. Branch - Answer-A. Load-and-store
Q6: Which stage is required for load and store operations?
5/5
A. I
B. E
C. D
D. all of the above - Answer-D. all of the above
Q7: A ________ instruction can be used to account for data and branch delays. *
5/5
A. SUB
B. NOOP
C. JUMP
D. all of the above - Answer-B. NOOP
Q8: The instruction location immediately following the delayed branch is referred to as
the ________.
5/5
A. delay load
B. delay file
C. delay slot
D. delay register - Answer-C. delay slot
Q9: The _________ stage includes ALU operations, cache access, and register update.
5/5
A. decode
B. execute
C. fetch
D. write back - Answer-B. execute
Q10: The MIPS R4000 uses ________ bits for all internal and external data paths and
for addresses, registers, and the ALU.
5/5
A. 16
B. 32
C. 64
D. 128 - Answer-C. 64
Q11: All MIPS R series processor instructions are encoded in a single ________ word
format.
5/5
A. 4-bit
,B. 8-bit
C. 16-bit
D. 32-bit - Answer-D. 32-bit
Q12: A _________ architecture is one that makes use of more, and more fine-grained
pipeline stages.
5/5
A. parallel
B. superpipelined
C. superscalar
D. hybrid - Answer-B. superpipelined
Q13: The R4000 can have as many as _______ instructions in the pipeline at the same
time.
5/5
A. 8
B. 10
C. 5
D. 3 - Answer-A. 8
Q14: The R4000 pipeline stage where the instruction result is written back to the
register file is the __________ stage.
5/5
A. write back
B. tag check
C. data cache
D. instruction execute - Answer-A. write back
Q15: SPARC refers to an architecture defined by ________.
5/5
A. Microsoft
B. Apple
C. Sun Microsystems
D. IBM - Answer-C. Sun Microsystems
Q16: The _________ contains a word of data to be written to memory or the word most
recently read
5/5
A. MAR
B. PC
C. MBR
D. IR - Answer-C. MBR
Q17: The ________ determines the opcode and the operand specifiers.
5/5
A. decode instruction
, B. fetch operands
C. calculate operands
D. execute instruction - Answer-A. decode instruction
Q18: A ________ hazard occurs when there is a conflict in the access of an operand
location.
5/5
A. resource
B. data
C. structural
D. control - Answer-B. data
Q20: The _________ is a small cache memory associated with the instruction fetch
stage of the pipeline.
5/5
A. dynamic branch
B. loop table
C. branch history table
D. flag - Answer-C. branch history table
Q1: The superscalar approach can be used on __________ architecture.
5/5
A. RISC
B. CISC
C. neither RISC nor CISC
D. both RISC and CISC - Answer-D. both RISC and CISC
Q2: The essence of the ________ approach is the ability to execute instructions
independently and concurrently in different pipelines.
5/5
A. scalar
B. branch
C. superscalar
D. flow dependency - Answer-C. superscalar
Q3: Which of the following is a fundamental limitation to parallelism with which the
system must cope?
5/5
A. procedural dependency
B. resource conflicts
C. antidependency
D. all of the above - Answer-D. all of the above
Q4: The situation where the second instruction needs data produced by the first
instruction to execute is referred to as __________.
5/5
