CEA201 Exam Study Questions, All Solved 100% Correct
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The use of multiple processors on the same chip is referred to as __________ and provides the
potential to increase performance without increasing the clock rate.
a. multicore
b. GPU
c. data channels
d. MPC - ✔✔multicore
With the __________, Intel introduced the use of superscalar techniques that allow multiple
instructions to execute in parallel.
a. Core
b. 8080
c. 80486
d. Pentium - ✔✔Pentium
The __________ measures the ability of a computer to complete a single task.
a. clock speed
b. speed metric
c. execute cycle
d. cycle time - ✔✔speed metric
ARM processors are designed to meet the needs of _________.
a. embedded real-time systems
b. application platforms
c. secure applications
,d. all of the above - ✔✔all of the above
One increment, or pulse, of the system clock is referred to as a _________.
a. clock tick
b. cycle time
c. clock rate
d. cycle speed - ✔✔clock tick
The __________ are used to designate the source or destination of the data on the data bus.
a. system lines
b. data lines
c. control lines
d. address lines - ✔✔address lines
The von Neumann architecture is based on which concept?
a. data and instructions are stored in a single read-write memory
b. the contents of this memory are addressable by location
c. execution occurs in a sequential fashion
d. all of the above - ✔✔all of the above
The TL supports which of the following address spaces?
a. memory
b. I/O
c. message
d. all of the above - ✔✔all of the above
The interconnection structure must support which transfer?
,a. memory to processor
b. processor to memory
c. I/O to or from memory
d. all of the above - ✔✔all of the above
The data lines provide a path for moving data among system modules and are collectively called
the _________.
a. control bus
b. address bus
c. data bus
d. system bus - ✔✔data bus
A(n) _________ is generated by a failure such as power failure or memory parity error.
a. I/O interrupt
b. hardware failure interrupt
c. timer interrupt
d. program interrupt - ✔✔hardware failure interrupt
The processing required for a single instruction is called a(n) __________ cycle.
a. execute
b. fetch
c. instruction
d. packet - ✔✔instruction
Virtually all contemporary computer designs are based on concepts developed by __________
at the Institute for Advanced Studies, Princeton.
a. John Maulchy
b. John von Neumann
, c. Herman Hollerith
d. John Eckert - ✔✔John von Neumann
Each data path consists of a pair of wires (referred to as a __________) that transmits data one
bit at a time.
a. lane
b. path
c. line
d. bus - ✔✔lane
A(n) _________ is generated by some condition that occurs as a result of an instruction
execution.
a. timer interrupt
b. I/O interrupt
c. program interrupt
d. hardware failure interrupt - ✔✔program interrupt
A __________ is the high-level set of rules for exchanging packets of data between devices.
a. bus
b. protocol
c. packet
d. QPI - ✔✔protocol
The QPI _________ layer is used to determine the course that a packet will traverse across the
available system interconnects.
a. link
b. protocol
c. routing
| Verified Answers | Pass Guaranteed
The use of multiple processors on the same chip is referred to as __________ and provides the
potential to increase performance without increasing the clock rate.
a. multicore
b. GPU
c. data channels
d. MPC - ✔✔multicore
With the __________, Intel introduced the use of superscalar techniques that allow multiple
instructions to execute in parallel.
a. Core
b. 8080
c. 80486
d. Pentium - ✔✔Pentium
The __________ measures the ability of a computer to complete a single task.
a. clock speed
b. speed metric
c. execute cycle
d. cycle time - ✔✔speed metric
ARM processors are designed to meet the needs of _________.
a. embedded real-time systems
b. application platforms
c. secure applications
,d. all of the above - ✔✔all of the above
One increment, or pulse, of the system clock is referred to as a _________.
a. clock tick
b. cycle time
c. clock rate
d. cycle speed - ✔✔clock tick
The __________ are used to designate the source or destination of the data on the data bus.
a. system lines
b. data lines
c. control lines
d. address lines - ✔✔address lines
The von Neumann architecture is based on which concept?
a. data and instructions are stored in a single read-write memory
b. the contents of this memory are addressable by location
c. execution occurs in a sequential fashion
d. all of the above - ✔✔all of the above
The TL supports which of the following address spaces?
a. memory
b. I/O
c. message
d. all of the above - ✔✔all of the above
The interconnection structure must support which transfer?
,a. memory to processor
b. processor to memory
c. I/O to or from memory
d. all of the above - ✔✔all of the above
The data lines provide a path for moving data among system modules and are collectively called
the _________.
a. control bus
b. address bus
c. data bus
d. system bus - ✔✔data bus
A(n) _________ is generated by a failure such as power failure or memory parity error.
a. I/O interrupt
b. hardware failure interrupt
c. timer interrupt
d. program interrupt - ✔✔hardware failure interrupt
The processing required for a single instruction is called a(n) __________ cycle.
a. execute
b. fetch
c. instruction
d. packet - ✔✔instruction
Virtually all contemporary computer designs are based on concepts developed by __________
at the Institute for Advanced Studies, Princeton.
a. John Maulchy
b. John von Neumann
, c. Herman Hollerith
d. John Eckert - ✔✔John von Neumann
Each data path consists of a pair of wires (referred to as a __________) that transmits data one
bit at a time.
a. lane
b. path
c. line
d. bus - ✔✔lane
A(n) _________ is generated by some condition that occurs as a result of an instruction
execution.
a. timer interrupt
b. I/O interrupt
c. program interrupt
d. hardware failure interrupt - ✔✔program interrupt
A __________ is the high-level set of rules for exchanging packets of data between devices.
a. bus
b. protocol
c. packet
d. QPI - ✔✔protocol
The QPI _________ layer is used to determine the course that a packet will traverse across the
available system interconnects.
a. link
b. protocol
c. routing
