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1





SOLUTIONS MANUAL







DIGITAL
DESIGN

WITH
AN
INTRODUCTION
TO
THE
VERILOG
HDL

Fifth
Edition










M.
MORRIS
MANO

Professor
Emeritus

California
State
University,
Los
Angeles




MICHAEL
D.
CILETTI

Professor
Emeritus



University
of
Colorado,
Colorado
Springs




rev
02/14/2012







Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,


All
rights
reserved.


,
2





CHAPTER 1

1.1 Base-10: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Octal: 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 40
Hex: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
Base-12 14 15 16 17 18 19 1A 1B 20 21 22 23 24 25 26 27 28

1.2 (a) 32,768 (b) 67,108,864 (c) 6,871,947,674

1.3 (4310)5 = 4 * 5 + 3 * 5 + 1 * 51 = 58010
3 2



(198)12 = 1 * 122 + 9 * 121 + 8 * 120 = 26010




(435)8
=
4
*
82
+
3
*
81
+
5
*
80
=
28510






(345)6
=
3
*
62
+
4
*
61
+
5
*
60
=
13710



1.4 16-bit binary: 1111_1111_1111_1111
Decimal equivalent: 216 -1 = 65,53510
Hexadecimal equivalent: FFFF16


1.5 Let b = base

(a) 14/2 = (b + 4)/2 = 5, so b = 6

(b) 54/4 = (5*b + 4)/4 = b + 3, so 5 * b = 52 – 4, and b = 8

(c) (2 *b + 4) + (b + 7) = 4b, so b = 11

1.6 (x – 3)(x – 6) = x2 –(6 + 3)x + 6*3 = x2 -11x + 22

Therefore: 6 + 3 = b + 1m, so b = 8
Also, 6*3 = (18)10 = (22)8


1.7 64CD16 = 0110_0100_1100_11012 = 110_010_011_001 _101 = (62315 )8


1.8 (a) Results of repeated division by 2 (quotients are followed by remainders):

43110 = 215(1); 107(1); 53(1); 26(1); 13(0); 6(1) 3(0) 1(1)
Answer: 1111_10102 = FA16

(b) Results of repeated division by 16:

43110 = 26(15); 1(10) (Faster)
Answer: FA = 1111_1010

1.9 (a) 10110.01012 = 16 + 4 + 2 + .25 + .0625 = 22.3125

(b) 16.516 = 16 + 6 + 5*(.0615) = 22.3125

(c) 26.248 = 2 * 8 + 6 + 2/8 + 4/64 = 22.3125

(d) DADA.B16 = 14*163 + 10*162 + 14*16 + 10 + 11/16 = 60,138.6875


Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,


All
rights
reserved.


,
3




(e) 1010.11012 = 8 + 2 + .5 + .25 + .0625 = 10.8125


1.10 (a) 1.100102 = 0001.10012 = 1.916 = 1 + 9/16 = 1.56310

(b) 110.0102 = 0110.01002 = 6.416 = 6 + 4/16 = 6.2510


Reason: 110.0102 is the same as 1.100102 shifted to the left by two places.








1011.11
1.11 101 | 111011.0000
101
01001
101
1001
101
1000
101
0110

The quotient is carried to two decimal places, giving 1011.11
Checking: = ≅ 1011.112 = 58.7510

1.12 (a) 10000 and 110111

1011 1011
+101 x101
10000 = 1610 1011
1011
110111 = 5510
(b) 62h and 958h

2Eh 0010_1110 2Eh
+34 h 0011_0100 x34h
62h 0110_0010 = 9810 B 38
2
8A
9 5 8h = 239210



1.13 (a) Convert 27.315 to binary:


Integer Remainder Coefficient
Quotient
27/2 = 13 + ½ a0 = 1
13/2 6 + ½ a1 = 1
6/2 3 + 0 a2 = 0
3/2 1 + ½ a3 = 1
½ 0 + ½ a4 = 1




Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,


All
rights
reserved.


,
4



2710 = 110112
Integer Fraction Coefficient
.315 x 2 = 0 + .630 a-1 = 0
.630 x 2 = 1 + .26 a-2 = 1
.26 x 2 = 0 + .52 a-3 = 0
.52 x 2 = 1 + .04 a-4 = 1

.31510 ≅ .01012 = .25 + .0625 = .3125

27.315 ≅ 11011.01012

(b) 2/3 ≅ .6666666667
Integer Fraction Coefficient
.6666_6666_67 x 2 = 1 + .3333_3333_34 a-1 = 1
.3333333334 x 2 = 0 + .6666666668 a-2 = 0
.6666666668 x 2 = 1 + .3333333336 a-3 = 1
.3333333336 x 2 = 0 + .6666666672 a-4 = 0
.6666666672 x 2 = 1 + .3333333344 a-5 = 1
.3333333344 x 2 = 0 + .6666666688 a-6 = 0
.6666666688 x 2 = 1 + .3333333376 a-7 = 1
.3333333376 x 2 = 0 + .6666666752 a-8 = 0

.666666666710 ≅ .101010102 = .5 + .125 + .0313 + ..0078 = .664110

.101010102 = .1010_10102 = .AA16 = 10/16 + 10/256 = .664110 (Same as (b)).

1.14 (a) 0001_0000 (b) 0000_0000 (c) 1101_1010
1s comp: 1110_1111 1s comp: 1111_1111 1s comp: 0010_0101
2s comp: 1111_0000 2s comp: 0000_0000 2s comp: 0010_0110

(d) 1010_1010 (e) 1000_0101 (f) 1111_1111
1s comp: 0101_0101 1s comp: 0111_1010 1s comp: 0000_0000
2s comp: 0101_0110 2s comp: 0111_1011 2s comp: 0000_0001
`
1.15 (a) 25,478,036 (b) 63,325,600
9s comp: 74,521,963 9s comp: 36,674,399
10s comp: 74,521,964 10s comp: 36,674,400


(c) 25,000,000 (d) 00000000
9s comp: 74,999,999 9s comp: 99999999
10s comp: 75,000,000 10s comp: 100000000


1.16 C3DF C3DF: 1100_0011_1101_1111
15s comp: 3C20 1s comp: 0011_1100_0010_0000
16s comp: 3C21 2s comp: 0011_1100_0010_0001 = 3C21

1.17 (a) 2,579 → 02,579 →97,420 (9s comp) → 97,421 (10s comp)
4637 – 2,579 = 2,579 + 97,421 = 205810

(b) 1800 → 01800 → 98199 (9s comp) → 98200 (10 comp)
125 – 1800 = 00125 + 98200 = 98325 (negative)
Magnitude: 1675
Result: 125 – 1800 = 1675




Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,


All
rights
reserved.