Samenvatting Computersystemen 1 - theorie hardware periode 2

HARDWARE P2




KDG | 2021-22

,Inhoudsopgave

4. Booleaanse algebra ........................................................................................................4
4.6 Tabellen omzetten naar formules .................................................................................... 4
4.6.1 De normaalvorm ........................................................................................................ 4
4.6.2 Programmmable logic arrays (PLA) ........................................................................... 5
4.6.3 Karnaugh kaarten ...................................................................................................... 5
4.6.4 Don’t care toestanden................................................................................................ 7

5. Veel voorkomende logische schakelingen........................................................................8
5.1 Multiplexer (MUX)............................................................................................................ 8
5.2 Demultiplexer (demux) .................................................................................................. 10
5.3 Half adder ....................................................................................................................... 11
5.4 Full adder........................................................................................................................ 11
5.5 Vergelijker (comparator) ................................................................................................ 12

6. Sequentiële schakelingen .............................................................................................. 14
6.1 RS latch ........................................................................................................................... 14
6.2 De synchrone RS latch .................................................................................................... 15
6.3 De synchrone D-latch ..................................................................................................... 16
6.4 De master-slave D flip-flop ............................................................................................. 17
6.5 De T flip-flop ................................................................................................................... 19

7. Veel voorkomende sequentiële schakelingen ................................................................ 19
7.1 Tellers ............................................................................................................................. 19
7.2 Registers ......................................................................................................................... 20
7.3 Shift-registers ................................................................................................................. 20

8. Tri-state buffers ............................................................................................................ 21
8.1 Het probleem ................................................................................................................. 21
8.2 De oplossing ................................................................................................................... 22
8.3 (static) RAM geheugen ................................................................................................... 24

9. De processor ................................................................................................................. 26
9.1 De opbouw ..................................................................................................................... 26



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, 9.2 De instructieset .............................................................................................................. 27
9.3 De compiler .................................................................................................................... 29
9.3.1 Variabalen en rekenen ............................................................................................. 30
9.3.2 Selectie ..................................................................................................................... 31
9.3.3 Iteratie ..................................................................................................................... 33
9.3.4 Speciale constructies ................................................................................................ 34
9.4 De onderdelen van de processor ................................................................................... 37
9.4.1 De bussen ................................................................................................................. 38
9.4.2 De registers .............................................................................................................. 38
9.4.3 De ALU ..................................................................................................................... 39
9.4.4 De control logic ........................................................................................................ 40
9.5 Arrays in assembler ........................................................................................................ 42
9.5 Uitleg videos assembler ................................................................................................. 43

10. Processoren in de praktijk ........................................................................................... 47
10.1 De Von Neumann architectuur .................................................................................... 47
10.2 De Modified Harvard architecture ............................................................................... 49
10.3 Registers ....................................................................................................................... 50
10.4 Adresbus, databus, controlebus ................................................................................... 50
10.5 Little en Big endian ....................................................................................................... 52
10.6 De stack pointer ........................................................................................................... 52
10.7 Interrupts ..................................................................................................................... 54
10.8 CISC en RISC processoren ............................................................................................. 55
10.9 Lengte van instructie .................................................................................................... 56
10.10 Co-processoren .......................................................................................................... 57
10.11 Multi-processing......................................................................................................... 57
10.11.1 Verschillende modes ............................................................................................ 58
10.11.2 Hyperthreading .................................................................................................... 58
10.11.3 Virtualisatie .......................................................................................................... 58
10.12 MMX (SIMD) instructies ............................................................................................. 59
10.13 Bugs in de hardware................................................................................................... 59
10.14 Caching ....................................................................................................................... 60
10.15 Power management ................................................................................................... 60



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, 10.16 Pipelining .................................................................................................................... 61
10.17 Multi-core processoren .............................................................................................. 63
10.18 Evolutie....................................................................................................................... 64




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