WGU C952 Computer Architecture - Complete Exam Prep
Document | 2026/2027 Edition | 100 Verified Questions
WGU C952 Computer Architecture Exam 2026-2027 QUESTIONS AND ANSWERS
ALREADY GRADED A+. 100% Verified Solutions | Updated Per Latest Guidelines | Graded A+
This comprehensive exam preparation resource covers all three parts of the WGU C952 Computer
Architecture exam, featuring 100 verified multiple-choice questions with detailed answers. Designed to
guarantee a passing grade, this guide provides thorough coverage of key topics including processor
architecture, memory hierarchy, and I/O systems. Each question is accompanied by rationales and
distractor explanations to reinforce understanding. Updated for the 2026/2027 academic year, this
document is an essential tool for mastering computer architecture concepts.
Key Features:
Processor architecture and pipelining
Memory hierarchy including cache and virtual memory
I/O systems and storage technologies
Instruction set architectures and performance metrics
Parallel processing and multi-core systems
Control unit design and microprogramming
Updates for 2026:
- Updated to reflect the latest WGU C952 exam blueprint for 2026/2027
- Added new questions on modern processor technologies
- Revised answer rationales for clarity and accuracy
- Enhanced distractor explanations to address common misconceptions
- Included performance analysis examples with current benchmarks
Abstract:
This document provides a rigorous preparation tool for the WGU C952 Computer Architecture exam,
encompassing all three parts of the assessment. It contains 100 multiple-choice questions that have been verified
for accuracy and relevance to the 2026/2027 academic year. Each question is designed to test critical knowledge
areas such as processor design, memory systems, I/O operations, and performance evaluation. The answers
include detailed rationales that explain why each option is correct or incorrect, facilitating deep learning.
Additionally, the guide covers advanced topics like pipelining hazards, cache coherence protocols, and parallel
architectures. By systematically working through these questions, students can identify knowledge gaps and
reinforce their understanding. This resource is aligned with the latest exam guidelines and is intended to ensure a
high level of preparedness. The content is presented in a structured format that mirrors the actual exam
experience, making it an invaluable study aid.
Keywords:
WGU C952, Computer Architecture, Exam Prep, Multiple Choice Questions, Processor Architecture, Memory
Hierarchy, I/O Systems, Performance Metrics
Answer Format:
Each question is followed by the correct answer and a detailed rationale explaining the underlying concepts.
Incorrect options are accompanied by distractor explanations that clarify common errors and misconceptions,
ensuring comprehensive understanding.
Compliance Checklist:
All questions verified against WGU C952 exam objectives
Page 1
, Answers and rationales reviewed by subject matter experts
Content updated to reflect 2026/2027 academic year guidelines
Formatting consistent with standard exam prep documents
Includes performance metrics and modern architecture examples
Content Area Overview:
Content Area Questions Key Topics Weight
Processor Architecture 1-25 Datapath design, pipelining, hazards, control 25%
unit
Memory Hierarchy 26-50 Cache memory, virtual memory, memory 25%
management, performance
I/O Systems and Storage 51-70 I/O interfaces, storage technologies, RAID, 20%
interrupts
Instruction Set Architecture 71-85 ISA design, addressing modes, instruction 15%
formats, RISC vs CISC
Parallel and Multi-core Systems 86-100 Parallel processing, multi-core architectures, 15%
cache coherence, synchronization
Page 2
, Q1. A processor has a 5-stage pipeline (IF, ID, EX, MEM, WB) with no forwarding hardware. A branch
instruction is resolved in the MEM stage. Assuming branches are always taken and the branch target is
known at the ID stage, what is the branch penalty in cycles for a correctly predicted taken branch?
A. 1 cycle
B. 2 cycles
C. 3 cycles
D. 4 cycles
Correct Answer: B. 2 cycles
Rationale: The branch is resolved in MEM, but the target is known in ID. Without forwarding, the branch
condition is computed in EX, so the next PC is known after EX. However, the instruction after the branch is fetched
in the next cycle, so the penalty is 2 cycles (the instruction after the branch is flushed, and the branch target is
fetched in the cycle after that).
Why Wrong:
A - A 1-cycle penalty would require the branch to be resolved earlier, e.g., in ID, which is not the case here.
C - A 3-cycle penalty would occur if the branch were resolved later, e.g., in MEM, but the target is known
earlier.
D - A 4-cycle penalty is too high; it would imply a deeper pipeline or more stalls.
Reference: Patterson & Hennessy, Computer Organization and Design, 5th Ed., Ch. 4
Q2. In a superscalar processor with out-of-order execution, which of the following techniques is primarily
used to resolve name dependencies (WAW and WAR hazards) without stalling the pipeline?
A. Register renaming
B. Speculative execution
C. Branch prediction
D. Memory disambiguation
Correct Answer: A. Register renaming
Rationale: Register renaming eliminates name dependencies by mapping architectural registers to physical
registers, allowing multiple instructions to use the same architectural register without conflict. Speculative
execution handles control hazards, branch prediction reduces branch penalties, and memory disambiguation
resolves memory ordering issues.
Why Wrong:
B - Speculative execution addresses control hazards, not name dependencies.
C - Branch prediction is for control hazards, not name dependencies.
D - Memory disambiguation deals with memory dependencies, not register name dependencies.
Reference: Hennessy & Patterson, Computer Architecture: A Quantitative Approach, 6th Ed., Ch. 3
Q3. A direct-mapped cache has 64 blocks, each block is 16 bytes. The main memory is byte-addressable with
32-bit addresses. How many bits are used for the tag, index, and offset fields?
A. Tag: 22, Index: 6, Offset: 4
B. Tag: 20, Index: 6, Offset: 4
C. Tag: 22, Index: 5, Offset: 4
D. Tag: 20, Index: 5, Offset: 4
Correct Answer: A. Tag: 22, Index: 6, Offset: 4
Rationale: Block size = 16 bytes => offset bits = log2(16) = 4. Number of blocks = 64 => index bits = log2(64) =
6. Address size = 32 bits => tag bits = 32 - 6 - 4 = 22. Thus, tag=22, index=6, offset=4.
Why Wrong:
B - Tag=20 would require more index or offset bits, but 6+4=10, leaving 22 for tag.
C - Index=5 would allow only 32 blocks, not 64.
D - Both tag and index are incorrect; index must be 6 for 64 blocks.
Page 3
Document | 2026/2027 Edition | 100 Verified Questions
WGU C952 Computer Architecture Exam 2026-2027 QUESTIONS AND ANSWERS
ALREADY GRADED A+. 100% Verified Solutions | Updated Per Latest Guidelines | Graded A+
This comprehensive exam preparation resource covers all three parts of the WGU C952 Computer
Architecture exam, featuring 100 verified multiple-choice questions with detailed answers. Designed to
guarantee a passing grade, this guide provides thorough coverage of key topics including processor
architecture, memory hierarchy, and I/O systems. Each question is accompanied by rationales and
distractor explanations to reinforce understanding. Updated for the 2026/2027 academic year, this
document is an essential tool for mastering computer architecture concepts.
Key Features:
Processor architecture and pipelining
Memory hierarchy including cache and virtual memory
I/O systems and storage technologies
Instruction set architectures and performance metrics
Parallel processing and multi-core systems
Control unit design and microprogramming
Updates for 2026:
- Updated to reflect the latest WGU C952 exam blueprint for 2026/2027
- Added new questions on modern processor technologies
- Revised answer rationales for clarity and accuracy
- Enhanced distractor explanations to address common misconceptions
- Included performance analysis examples with current benchmarks
Abstract:
This document provides a rigorous preparation tool for the WGU C952 Computer Architecture exam,
encompassing all three parts of the assessment. It contains 100 multiple-choice questions that have been verified
for accuracy and relevance to the 2026/2027 academic year. Each question is designed to test critical knowledge
areas such as processor design, memory systems, I/O operations, and performance evaluation. The answers
include detailed rationales that explain why each option is correct or incorrect, facilitating deep learning.
Additionally, the guide covers advanced topics like pipelining hazards, cache coherence protocols, and parallel
architectures. By systematically working through these questions, students can identify knowledge gaps and
reinforce their understanding. This resource is aligned with the latest exam guidelines and is intended to ensure a
high level of preparedness. The content is presented in a structured format that mirrors the actual exam
experience, making it an invaluable study aid.
Keywords:
WGU C952, Computer Architecture, Exam Prep, Multiple Choice Questions, Processor Architecture, Memory
Hierarchy, I/O Systems, Performance Metrics
Answer Format:
Each question is followed by the correct answer and a detailed rationale explaining the underlying concepts.
Incorrect options are accompanied by distractor explanations that clarify common errors and misconceptions,
ensuring comprehensive understanding.
Compliance Checklist:
All questions verified against WGU C952 exam objectives
Page 1
, Answers and rationales reviewed by subject matter experts
Content updated to reflect 2026/2027 academic year guidelines
Formatting consistent with standard exam prep documents
Includes performance metrics and modern architecture examples
Content Area Overview:
Content Area Questions Key Topics Weight
Processor Architecture 1-25 Datapath design, pipelining, hazards, control 25%
unit
Memory Hierarchy 26-50 Cache memory, virtual memory, memory 25%
management, performance
I/O Systems and Storage 51-70 I/O interfaces, storage technologies, RAID, 20%
interrupts
Instruction Set Architecture 71-85 ISA design, addressing modes, instruction 15%
formats, RISC vs CISC
Parallel and Multi-core Systems 86-100 Parallel processing, multi-core architectures, 15%
cache coherence, synchronization
Page 2
, Q1. A processor has a 5-stage pipeline (IF, ID, EX, MEM, WB) with no forwarding hardware. A branch
instruction is resolved in the MEM stage. Assuming branches are always taken and the branch target is
known at the ID stage, what is the branch penalty in cycles for a correctly predicted taken branch?
A. 1 cycle
B. 2 cycles
C. 3 cycles
D. 4 cycles
Correct Answer: B. 2 cycles
Rationale: The branch is resolved in MEM, but the target is known in ID. Without forwarding, the branch
condition is computed in EX, so the next PC is known after EX. However, the instruction after the branch is fetched
in the next cycle, so the penalty is 2 cycles (the instruction after the branch is flushed, and the branch target is
fetched in the cycle after that).
Why Wrong:
A - A 1-cycle penalty would require the branch to be resolved earlier, e.g., in ID, which is not the case here.
C - A 3-cycle penalty would occur if the branch were resolved later, e.g., in MEM, but the target is known
earlier.
D - A 4-cycle penalty is too high; it would imply a deeper pipeline or more stalls.
Reference: Patterson & Hennessy, Computer Organization and Design, 5th Ed., Ch. 4
Q2. In a superscalar processor with out-of-order execution, which of the following techniques is primarily
used to resolve name dependencies (WAW and WAR hazards) without stalling the pipeline?
A. Register renaming
B. Speculative execution
C. Branch prediction
D. Memory disambiguation
Correct Answer: A. Register renaming
Rationale: Register renaming eliminates name dependencies by mapping architectural registers to physical
registers, allowing multiple instructions to use the same architectural register without conflict. Speculative
execution handles control hazards, branch prediction reduces branch penalties, and memory disambiguation
resolves memory ordering issues.
Why Wrong:
B - Speculative execution addresses control hazards, not name dependencies.
C - Branch prediction is for control hazards, not name dependencies.
D - Memory disambiguation deals with memory dependencies, not register name dependencies.
Reference: Hennessy & Patterson, Computer Architecture: A Quantitative Approach, 6th Ed., Ch. 3
Q3. A direct-mapped cache has 64 blocks, each block is 16 bytes. The main memory is byte-addressable with
32-bit addresses. How many bits are used for the tag, index, and offset fields?
A. Tag: 22, Index: 6, Offset: 4
B. Tag: 20, Index: 6, Offset: 4
C. Tag: 22, Index: 5, Offset: 4
D. Tag: 20, Index: 5, Offset: 4
Correct Answer: A. Tag: 22, Index: 6, Offset: 4
Rationale: Block size = 16 bytes => offset bits = log2(16) = 4. Number of blocks = 64 => index bits = log2(64) =
6. Address size = 32 bits => tag bits = 32 - 6 - 4 = 22. Thus, tag=22, index=6, offset=4.
Why Wrong:
B - Tag=20 would require more index or offset bits, but 6+4=10, leaving 22 for tag.
C - Index=5 would allow only 32 blocks, not 64.
D - Both tag and index are incorrect; index must be 6 for 64 blocks.
Page 3
