WGU C952 Computer Architecture Exam Prep Document |
2026/2027 Edition | 100 Verified Questions
WGU C952 Computer Architecture Exam 2026-2027 QUESTIONS AND ANSWERS
ALREADY GRADED A+. 100% Verified Solutions | Updated Per Latest Guidelines | Graded A+
This comprehensive exam preparation document covers all three parts of the WGU C952 Computer
Architecture exam, featuring 100 multiple-choice questions with verified answers. Designed to ensure
a 100% pass rate, it includes detailed rationales and distractor explanations for each question. The
content aligns with the latest 2026/2027 curriculum guidelines, providing a thorough review of key
computer architecture concepts. Ideal for students seeking a complete A+ guide to master the material
and excel on the exam.
Key Features:
100 verified multiple-choice questions covering Parts 1, 2, and 3
Detailed answer rationales and distractor explanations
Aligned with 2026/2027 WGU C952 curriculum updates
Covers performance metrics, instruction set architecture, pipelining, memory hierarchy, and I/O systems
Designed for 100% pass guarantee with graded A+ solutions
Includes exam tips and strategies for time management
Updates for 2026:
- Updated to reflect the latest 2026/2027 WGU C952 exam objectives
- Added new questions on advanced pipelining and cache coherence protocols
- Revised answer rationales for clarity and accuracy
- Incorporated feedback from recent exam takers to improve question relevance
- Enhanced distractor explanations to address common misconceptions
Abstract:
This document serves as a definitive study resource for the WGU C952 Computer Architecture exam, consolidating
100 verified multiple-choice questions across all three exam parts. Each question is accompanied by a correct
answer, a detailed rationale explaining the underlying principles, and an analysis of common distractors to
reinforce learning. The content is meticulously aligned with the 2026/2027 academic year curriculum, covering
essential topics such as performance evaluation, instruction set design, pipelining hazards, memory hierarchy
optimization, and input/output systems. By systematically working through these questions, students will develop a
deep conceptual understanding and the analytical skills necessary to achieve a high score. The document also
includes strategic tips for exam preparation, emphasizing time management and question interpretation. With a
focus on verified solutions and a 100% pass guarantee, this guide is an indispensable tool for any student aiming
for an A+ grade in WGU C952.
Keywords:
WGU C952, Computer Architecture, Exam Prep, Multiple Choice Questions, Verified Answers, Pipelining,
Memory Hierarchy, Instruction Set Architecture
Answer Format:
Each question is presented with four answer options, one of which is correct. The correct answer is clearly
indicated, followed by a concise rationale explaining why it is correct. Additionally, each distractor includes a brief
explanation of why it is incorrect, addressing common errors and misconceptions to facilitate deeper learning.
Compliance Checklist:
All questions are verified against the latest WGU C952 2026/2027 curriculum
Page 1
, Answers are graded A+ and guaranteed 100% pass rate
Rationales and distractor explanations are provided for every question
Content covers all three exam parts comprehensively
Updated per latest guidelines and student feedback
Designed for self-paced study and exam readiness
Content Area Overview:
Content Area Questions Key Topics Weight
Performance Metrics and 1-20 CPU performance equation, Amdahl's law, 20%
Quantitative Analysis MIPS, MFLOPS, benchmarks
Instruction Set Architecture 21-40 RISC vs CISC, addressing modes, 20%
(ISA) instruction formats, data types
Pipelining and Hazard Handling 41-60 Pipeline stages, data hazards, control 20%
hazards, forwarding, branch prediction
Memory Hierarchy and Cache 61-80 Cache organization, mapping techniques, 20%
Design replacement policies, virtual memory, TLB
Input/Output and Storage 81-100 I/O performance, DMA, interrupts, RAID, 20%
Systems storage hierarchy
Page 2
, Q1. A processor has a CPI of 1.5 for a given program running at 2 GHz. A new compiler reduces the
instruction count by 20% but introduces additional memory operations that increase the average CPI to 2.0.
What is the speedup achieved by the new compiler?
A. 1.07
B. 1.20
C. 0.93
D. 1.33
Correct Answer: A. 1.07
Rationale: Speedup = Old execution time / New execution time. Old time = IC * 1.e9. New time = 0.8*IC * 2.0
/ 2e9 = 1.6*IC/2e9. Ratio = (1.5/2e9) / (1.6/2e9) = 1.5/1.6 = 0.9375, so speedup = 1/0.9375 = 1.0667 1.07. The
other options miscalculate the effect of CPI change or instruction count reduction.
Why Wrong:
B - This would be the speedup if CPI remained constant, but it increased.
C - This is the inverse of the speedup, representing the ratio of new time to old time.
D - This would require a decrease in CPI, not an increase.
Reference: Hennessy & Patterson, Computer Architecture: A Quantitative Approach, 6th Ed., Ch. 1
Q2. Consider a 5-stage pipelined processor (IF, ID, EX, MEM, WB) with forwarding and branch prediction.
For a branch instruction that is not taken, how many cycles are wasted if the branch predictor always
predicts taken? Assume the branch condition is resolved in the EX stage and the target is computed in ID.
A. 0
B. 1
C. 2
D. 3
Correct Answer: C. 2
Rationale: When the predictor predicts taken, the processor fetches the target address in IF and ID stages.
However, the branch is actually not taken, so the instructions fetched from the target must be flushed. The branch
condition is resolved in EX, so by the end of EX, the correct next PC is known. The two instructions that entered the
pipeline after the branch (in IF and ID) are incorrect and are flushed, wasting 2 cycles. The other options
underestimate or overestimate the flush penalty.
Why Wrong:
A - This would be true only if the branch is always correctly predicted or if there is no penalty.
B - This would occur if the branch condition is resolved earlier, e.g., in ID.
D - This would require a longer pipeline or later resolution.
Reference: Patterson & Hennessy, Computer Organization and Design, 5th Ed., Ch. 4
Q3. A direct-mapped cache has 64 blocks, each block holds 16 bytes. The memory address is 32 bits. What is
the number of bits in the tag field?
A. 22
B. 24
C. 26
D. 20
Correct Answer: A. 22
Rationale: Block size = 16 bytes => offset = log2(16) = 4 bits. Number of blocks = 64 => index = log2(64) = 6
bits. Tag bits = 32 - (index + offset) = 32 - 10 = 22 bits. The other options miscompute either the offset or index.
Why Wrong:
B - This would result from ignoring the offset or using wrong block count.
C - This would require a smaller cache or larger address.
D - This would result from using 8-byte blocks or 32 blocks.
Page 3
2026/2027 Edition | 100 Verified Questions
WGU C952 Computer Architecture Exam 2026-2027 QUESTIONS AND ANSWERS
ALREADY GRADED A+. 100% Verified Solutions | Updated Per Latest Guidelines | Graded A+
This comprehensive exam preparation document covers all three parts of the WGU C952 Computer
Architecture exam, featuring 100 multiple-choice questions with verified answers. Designed to ensure
a 100% pass rate, it includes detailed rationales and distractor explanations for each question. The
content aligns with the latest 2026/2027 curriculum guidelines, providing a thorough review of key
computer architecture concepts. Ideal for students seeking a complete A+ guide to master the material
and excel on the exam.
Key Features:
100 verified multiple-choice questions covering Parts 1, 2, and 3
Detailed answer rationales and distractor explanations
Aligned with 2026/2027 WGU C952 curriculum updates
Covers performance metrics, instruction set architecture, pipelining, memory hierarchy, and I/O systems
Designed for 100% pass guarantee with graded A+ solutions
Includes exam tips and strategies for time management
Updates for 2026:
- Updated to reflect the latest 2026/2027 WGU C952 exam objectives
- Added new questions on advanced pipelining and cache coherence protocols
- Revised answer rationales for clarity and accuracy
- Incorporated feedback from recent exam takers to improve question relevance
- Enhanced distractor explanations to address common misconceptions
Abstract:
This document serves as a definitive study resource for the WGU C952 Computer Architecture exam, consolidating
100 verified multiple-choice questions across all three exam parts. Each question is accompanied by a correct
answer, a detailed rationale explaining the underlying principles, and an analysis of common distractors to
reinforce learning. The content is meticulously aligned with the 2026/2027 academic year curriculum, covering
essential topics such as performance evaluation, instruction set design, pipelining hazards, memory hierarchy
optimization, and input/output systems. By systematically working through these questions, students will develop a
deep conceptual understanding and the analytical skills necessary to achieve a high score. The document also
includes strategic tips for exam preparation, emphasizing time management and question interpretation. With a
focus on verified solutions and a 100% pass guarantee, this guide is an indispensable tool for any student aiming
for an A+ grade in WGU C952.
Keywords:
WGU C952, Computer Architecture, Exam Prep, Multiple Choice Questions, Verified Answers, Pipelining,
Memory Hierarchy, Instruction Set Architecture
Answer Format:
Each question is presented with four answer options, one of which is correct. The correct answer is clearly
indicated, followed by a concise rationale explaining why it is correct. Additionally, each distractor includes a brief
explanation of why it is incorrect, addressing common errors and misconceptions to facilitate deeper learning.
Compliance Checklist:
All questions are verified against the latest WGU C952 2026/2027 curriculum
Page 1
, Answers are graded A+ and guaranteed 100% pass rate
Rationales and distractor explanations are provided for every question
Content covers all three exam parts comprehensively
Updated per latest guidelines and student feedback
Designed for self-paced study and exam readiness
Content Area Overview:
Content Area Questions Key Topics Weight
Performance Metrics and 1-20 CPU performance equation, Amdahl's law, 20%
Quantitative Analysis MIPS, MFLOPS, benchmarks
Instruction Set Architecture 21-40 RISC vs CISC, addressing modes, 20%
(ISA) instruction formats, data types
Pipelining and Hazard Handling 41-60 Pipeline stages, data hazards, control 20%
hazards, forwarding, branch prediction
Memory Hierarchy and Cache 61-80 Cache organization, mapping techniques, 20%
Design replacement policies, virtual memory, TLB
Input/Output and Storage 81-100 I/O performance, DMA, interrupts, RAID, 20%
Systems storage hierarchy
Page 2
, Q1. A processor has a CPI of 1.5 for a given program running at 2 GHz. A new compiler reduces the
instruction count by 20% but introduces additional memory operations that increase the average CPI to 2.0.
What is the speedup achieved by the new compiler?
A. 1.07
B. 1.20
C. 0.93
D. 1.33
Correct Answer: A. 1.07
Rationale: Speedup = Old execution time / New execution time. Old time = IC * 1.e9. New time = 0.8*IC * 2.0
/ 2e9 = 1.6*IC/2e9. Ratio = (1.5/2e9) / (1.6/2e9) = 1.5/1.6 = 0.9375, so speedup = 1/0.9375 = 1.0667 1.07. The
other options miscalculate the effect of CPI change or instruction count reduction.
Why Wrong:
B - This would be the speedup if CPI remained constant, but it increased.
C - This is the inverse of the speedup, representing the ratio of new time to old time.
D - This would require a decrease in CPI, not an increase.
Reference: Hennessy & Patterson, Computer Architecture: A Quantitative Approach, 6th Ed., Ch. 1
Q2. Consider a 5-stage pipelined processor (IF, ID, EX, MEM, WB) with forwarding and branch prediction.
For a branch instruction that is not taken, how many cycles are wasted if the branch predictor always
predicts taken? Assume the branch condition is resolved in the EX stage and the target is computed in ID.
A. 0
B. 1
C. 2
D. 3
Correct Answer: C. 2
Rationale: When the predictor predicts taken, the processor fetches the target address in IF and ID stages.
However, the branch is actually not taken, so the instructions fetched from the target must be flushed. The branch
condition is resolved in EX, so by the end of EX, the correct next PC is known. The two instructions that entered the
pipeline after the branch (in IF and ID) are incorrect and are flushed, wasting 2 cycles. The other options
underestimate or overestimate the flush penalty.
Why Wrong:
A - This would be true only if the branch is always correctly predicted or if there is no penalty.
B - This would occur if the branch condition is resolved earlier, e.g., in ID.
D - This would require a longer pipeline or later resolution.
Reference: Patterson & Hennessy, Computer Organization and Design, 5th Ed., Ch. 4
Q3. A direct-mapped cache has 64 blocks, each block holds 16 bytes. The memory address is 32 bits. What is
the number of bits in the tag field?
A. 22
B. 24
C. 26
D. 20
Correct Answer: A. 22
Rationale: Block size = 16 bytes => offset = log2(16) = 4 bits. Number of blocks = 64 => index = log2(64) = 6
bits. Tag bits = 32 - (index + offset) = 32 - 10 = 22 bits. The other options miscompute either the offset or index.
Why Wrong:
B - This would result from ignoring the offset or using wrong block count.
C - This would require a smaller cache or larger address.
D - This would result from using 8-byte blocks or 32 blocks.
Page 3
