CS250: Foundation of Computer Systems Exam #1 Questions
with Correct Answers
True or False: Direct-mapped, fully associative, and k-way associative caching
schemes cache data in contiguous blocks of bytes (referred to as cache lines)
rather than bytes in isolation. - ✔✔True
True or False: A direct mapped cache can also be thought of as a zero-way
associative cache. - ✔✔False, a direct mapped cache is also known as a one-way
associative cache.
True or False: Cache eviction decisions in direct-mapped caches are far simpler
than those in fully associative caches. - ✔✔True, in direct mapped caches because
each memory block maps to only one cache line, where as fully associative cache
the memory block must place the cache line that has been there the longest.
Consider a direct mapped 8KB cache that is organized as 512 cache lines of 16
bytes each. For a 32-bit address space where the bits are numbered from 0
through 31, which bits in the address space are used to identify the cache line. -
✔✔9 bits (4 through 12) of the physical memory address provide an index to
select one of the 512 cache lines within the cache (2^9=512)
True or False: L1 and L2 caches are based on fully associative caching schemes
due to their superior load balancing schemes. - ✔✔False, the extra circuitry to
achieve full associativity is expensive and, worse, can slow down the memory
subsystem. (Most L1 and L2 caches are not fully associative for this reason)
True or False: Increasing the number of cache lines in each set (say, 128) is a
viable way to improve over the performance of direct-mapped caches. - ✔✔False
, True or False: During a program's execution, the caching hardware and the OS
working in convert with each other, dynamically move data between subsystems
(L1, L2, L3, and memory) as the set of oft-used and seldom-used data change. -
✔✔True
True or False: In the von Neumann architecture, when the CPU is called upon to
execute a program, the program's code will already reside in the computer's
system. - ✔✔True, think of the von Neumann architecture like a chef who has all
the ingredients ready in the kitchen before starting to cook - in this case, the CPU
already has the program's code available to execute.
Consider a system that has a cache and main memory. The cache access times are
2 ns and the main memory access times are 50 ns. What is the effective access
time if the cache hit is 97% and the data is found in main memory for the times
when it isn't in the cache. - ✔✔(2ns * 0.97) + (50ns * 0.03)
True or False: It is routine for CPU's to have hundreds of general purpose
registers. - ✔✔False, (e.g, x86-64 architecture has 16 general-purpose registers in
64-bit mode).
True or False: As a side effect of the instruction's execution, the CPU also figures
out which instruction to fetch and execute next. - ✔✔True, Think of the CPU like a
chef in a kitchen - after finishing one recipe (instruction), it automatically knows
which recipe (instruction) to start cooking next based on the flow of the meal
preparation.
True or False: Although it works well for several classes of problems, dividing up a
single program so that it can be parallelized to make use of multiple CPUs is an
unsolved problem in the general case. - ✔✔True, (Imagine trying to coordinate a
group of people to work on different parts of a project simultaneously without
with Correct Answers
True or False: Direct-mapped, fully associative, and k-way associative caching
schemes cache data in contiguous blocks of bytes (referred to as cache lines)
rather than bytes in isolation. - ✔✔True
True or False: A direct mapped cache can also be thought of as a zero-way
associative cache. - ✔✔False, a direct mapped cache is also known as a one-way
associative cache.
True or False: Cache eviction decisions in direct-mapped caches are far simpler
than those in fully associative caches. - ✔✔True, in direct mapped caches because
each memory block maps to only one cache line, where as fully associative cache
the memory block must place the cache line that has been there the longest.
Consider a direct mapped 8KB cache that is organized as 512 cache lines of 16
bytes each. For a 32-bit address space where the bits are numbered from 0
through 31, which bits in the address space are used to identify the cache line. -
✔✔9 bits (4 through 12) of the physical memory address provide an index to
select one of the 512 cache lines within the cache (2^9=512)
True or False: L1 and L2 caches are based on fully associative caching schemes
due to their superior load balancing schemes. - ✔✔False, the extra circuitry to
achieve full associativity is expensive and, worse, can slow down the memory
subsystem. (Most L1 and L2 caches are not fully associative for this reason)
True or False: Increasing the number of cache lines in each set (say, 128) is a
viable way to improve over the performance of direct-mapped caches. - ✔✔False
, True or False: During a program's execution, the caching hardware and the OS
working in convert with each other, dynamically move data between subsystems
(L1, L2, L3, and memory) as the set of oft-used and seldom-used data change. -
✔✔True
True or False: In the von Neumann architecture, when the CPU is called upon to
execute a program, the program's code will already reside in the computer's
system. - ✔✔True, think of the von Neumann architecture like a chef who has all
the ingredients ready in the kitchen before starting to cook - in this case, the CPU
already has the program's code available to execute.
Consider a system that has a cache and main memory. The cache access times are
2 ns and the main memory access times are 50 ns. What is the effective access
time if the cache hit is 97% and the data is found in main memory for the times
when it isn't in the cache. - ✔✔(2ns * 0.97) + (50ns * 0.03)
True or False: It is routine for CPU's to have hundreds of general purpose
registers. - ✔✔False, (e.g, x86-64 architecture has 16 general-purpose registers in
64-bit mode).
True or False: As a side effect of the instruction's execution, the CPU also figures
out which instruction to fetch and execute next. - ✔✔True, Think of the CPU like a
chef in a kitchen - after finishing one recipe (instruction), it automatically knows
which recipe (instruction) to start cooking next based on the flow of the meal
preparation.
True or False: Although it works well for several classes of problems, dividing up a
single program so that it can be parallelized to make use of multiple CPUs is an
unsolved problem in the general case. - ✔✔True, (Imagine trying to coordinate a
group of people to work on different parts of a project simultaneously without
