PVL2602 MCQ EXAM STUDY GUIDE 2026
QUESTIONS WITH SOLUTIONS GRADED A+
◉ Unsigned Integer Range (n bits). Answer: Range is 0 to (2ⁿ − 1). All
bits represent magnitude only.
◉ 2's Complement Overflow Rule. Answer: Overflow occurs when
adding two numbers of the SAME sign produces a result with a
DIFFERENT sign.
◉ Carry Bit vs Overflow. Answer: Carry bit does NOT determine
overflow in signed arithmetic; overflow depends on sign comparison.
◉ 2's Complement Subtraction Method. Answer: Subtraction is
performed by adding the two's complement of the subtrahend (invert +
1).
◉ NAND Gate Universality. Answer: Any logic gate (AND, OR, NOT)
can be built using only NAND gates.
◉ NOR Gate Universality. Answer: Any logic gate can be constructed
using only NOR gates.
, ◉ Instruction Set Architecture (ISA). Answer: The interface between
hardware and software that defines machine language, registers, and
operations.
◉ Positive + Negative Overflow Rule. Answer: Adding a positive and a
negative number cannot cause overflow.
◉ Boolean Simplification Concept. Answer: Use Boolean identities to
reduce expressions to minimal form (absorption, DeMorgan, distributive
laws).
◉ Boolean Function Simplification. Answer: Reduce logic expressions
using identities to remove redundant terms.
◉ Overflow Detection in 8-bit 2's Complement. Answer: Occurs when
adding two positives gives a negative or two negatives give a positive.
◉ Signed vs Unsigned Arithmetic. Answer: Signed considers MSB as
sign; unsigned treats all bits as magnitude.
◉ Two's Complement Representation Advantage. Answer: Only one
representation for zero, avoiding ambiguity of sign-magnitude.
◉ 1's Complement Zero Issue. Answer: Has two zeros (+0 and -0),
making it inefficient.
QUESTIONS WITH SOLUTIONS GRADED A+
◉ Unsigned Integer Range (n bits). Answer: Range is 0 to (2ⁿ − 1). All
bits represent magnitude only.
◉ 2's Complement Overflow Rule. Answer: Overflow occurs when
adding two numbers of the SAME sign produces a result with a
DIFFERENT sign.
◉ Carry Bit vs Overflow. Answer: Carry bit does NOT determine
overflow in signed arithmetic; overflow depends on sign comparison.
◉ 2's Complement Subtraction Method. Answer: Subtraction is
performed by adding the two's complement of the subtrahend (invert +
1).
◉ NAND Gate Universality. Answer: Any logic gate (AND, OR, NOT)
can be built using only NAND gates.
◉ NOR Gate Universality. Answer: Any logic gate can be constructed
using only NOR gates.
, ◉ Instruction Set Architecture (ISA). Answer: The interface between
hardware and software that defines machine language, registers, and
operations.
◉ Positive + Negative Overflow Rule. Answer: Adding a positive and a
negative number cannot cause overflow.
◉ Boolean Simplification Concept. Answer: Use Boolean identities to
reduce expressions to minimal form (absorption, DeMorgan, distributive
laws).
◉ Boolean Function Simplification. Answer: Reduce logic expressions
using identities to remove redundant terms.
◉ Overflow Detection in 8-bit 2's Complement. Answer: Occurs when
adding two positives gives a negative or two negatives give a positive.
◉ Signed vs Unsigned Arithmetic. Answer: Signed considers MSB as
sign; unsigned treats all bits as magnitude.
◉ Two's Complement Representation Advantage. Answer: Only one
representation for zero, avoiding ambiguity of sign-magnitude.
◉ 1's Complement Zero Issue. Answer: Has two zeros (+0 and -0),
making it inefficient.
