WGU C952 COMPUTER ARCHITECTURE -
SET 1 -5 EXAM 2026-2027 BANK
CURRENTLY TESTING COMPLETE EXAM
QUESTIONS WITH DETAILED VERIFIED
ANSWERS /EXPERT VERIFIED /ALREADY
GRADED A+
An expanded set of instructions supported by a processor
that provides multimedia-specific functions. -
....ANSWER...multimedia extensions (MMX)
When a planned instruction cannot execute in the proper
clock cycle because data that is needed to execute the
instruction are not yet available. - ....ANSWER...data
hazard (pipeline data hazard)
A method of resolving a data hazard by retrieving the
missing data element from internal buffers rather than
waiting for it to arrive from programmer-visible registers
or memory - ....ANSWER...forwarding (bypassing)
,When a planned instruction cannot execute in the proper
clock cycle because the hardware does not support the
combination of instructions that are set to execute. -
....ANSWER...Structural hazard
Technique that allows the CPU to work on more than one
instruction at a time
Formula
total process time = [longest task * (total load -1)] + total
load time - ....ANSWER...Pipelining
Requires register file and the ALU. - ....ANSWER...R-
format ALU operations
The register that contains the address of the next
instruction to be executed - ....ANSWER...Program
Counter (PC)
The results of the operation of any system. -
....ANSWER...output
,The principle stating that if a data location is referenced
then it will tend to be referenced again soon. -
....ANSWER...temporal locality
The principle stating that if a data location is referenced,
data locations with nearby addresses will tend to be
referenced soon. - ....ANSWER...spatial locality
A structure that uses multiple levels of memories; as the
distance from the processor increases, the size of the
memories and the access time both increase. -
....ANSWER...Memory hierarchy
The minimum unit of information that can be either
present or not present in a cache. - ....ANSWER...Block
(or line)
The fraction of memory accesses found in a level of the
memory hierarchy. - ....ANSWER...Hit rate
The fraction of memory accesses not found in a level of the
memory hierarchy - ....ANSWER...Miss rate
, The time required to fetch a block into a level of the
memory hierarchy from the lower level, including the time
to access the block, transmit it from one level to the other,
insert it in the level that experienced the miss, and then
pass the block to the requestor. - ....ANSWER...miss
penalty
The time required to access a level of the memory
hierarchy, including the time needed to determine whether
the access is a hit or a miss. - ....ANSWER...Hit time
consist of dividing a program into separate components
that run in parallel on individual computers in the cluster -
....ANSWER...Parallelization
Technique primarily associated with hardware.
Functional units (ALU, Floating Point Unit, Load/Store
Unit) are duplicated in the pipeline of a superscalar
processor which allows the hardware to issue multiple
instructions to each unit simultaneously. -
....ANSWER...superscalar
SET 1 -5 EXAM 2026-2027 BANK
CURRENTLY TESTING COMPLETE EXAM
QUESTIONS WITH DETAILED VERIFIED
ANSWERS /EXPERT VERIFIED /ALREADY
GRADED A+
An expanded set of instructions supported by a processor
that provides multimedia-specific functions. -
....ANSWER...multimedia extensions (MMX)
When a planned instruction cannot execute in the proper
clock cycle because data that is needed to execute the
instruction are not yet available. - ....ANSWER...data
hazard (pipeline data hazard)
A method of resolving a data hazard by retrieving the
missing data element from internal buffers rather than
waiting for it to arrive from programmer-visible registers
or memory - ....ANSWER...forwarding (bypassing)
,When a planned instruction cannot execute in the proper
clock cycle because the hardware does not support the
combination of instructions that are set to execute. -
....ANSWER...Structural hazard
Technique that allows the CPU to work on more than one
instruction at a time
Formula
total process time = [longest task * (total load -1)] + total
load time - ....ANSWER...Pipelining
Requires register file and the ALU. - ....ANSWER...R-
format ALU operations
The register that contains the address of the next
instruction to be executed - ....ANSWER...Program
Counter (PC)
The results of the operation of any system. -
....ANSWER...output
,The principle stating that if a data location is referenced
then it will tend to be referenced again soon. -
....ANSWER...temporal locality
The principle stating that if a data location is referenced,
data locations with nearby addresses will tend to be
referenced soon. - ....ANSWER...spatial locality
A structure that uses multiple levels of memories; as the
distance from the processor increases, the size of the
memories and the access time both increase. -
....ANSWER...Memory hierarchy
The minimum unit of information that can be either
present or not present in a cache. - ....ANSWER...Block
(or line)
The fraction of memory accesses found in a level of the
memory hierarchy. - ....ANSWER...Hit rate
The fraction of memory accesses not found in a level of the
memory hierarchy - ....ANSWER...Miss rate
, The time required to fetch a block into a level of the
memory hierarchy from the lower level, including the time
to access the block, transmit it from one level to the other,
insert it in the level that experienced the miss, and then
pass the block to the requestor. - ....ANSWER...miss
penalty
The time required to access a level of the memory
hierarchy, including the time needed to determine whether
the access is a hit or a miss. - ....ANSWER...Hit time
consist of dividing a program into separate components
that run in parallel on individual computers in the cluster -
....ANSWER...Parallelization
Technique primarily associated with hardware.
Functional units (ALU, Floating Point Unit, Load/Store
Unit) are duplicated in the pipeline of a superscalar
processor which allows the hardware to issue multiple
instructions to each unit simultaneously. -
....ANSWER...superscalar
