Sample Midterm 1
The following partial specifications are given:
Question 1.1
To determine the miss penalty (time to replace the block in cache) for the worst-case sce
block to be replaced always = 1) calculate the following:
• Bus clock period
• Bus transfer time
• Block replacement time (if D-bit = 1)
• Miss penalty
This question is just a matter of knowing the formula.
• The bus clock period is the reciprocal of the bus clock frequency.
1 1
tbus = = 6
≈ 7.5 × 10−9 s or 7.5 ns
fbus 133.33 × 10 Hz
Make sure you know the SI conversions, most notably for mega (M) and nano (n), as these will be those yo
tests.
• The block transfer time is the product of the number of words being transferred and the bus clock period.
Tbt = # of words × tbus = 32 words × 7.5 ns = 240 ns
• The block replacement time is given by the following formula.
, This is because it allows two data-words during one clock cycle period, so the block transfer gets cut in half. The r
the same.
Tmiss = Tbr = (80 ns + 120 ns)(2) + 10 ns = 410 ns
The system with DDR-SDRAM main memory has a miss penalty of 410 ns.
Question 1.3
Taking in account that average access time for the cache is equal to: Hit rate × Hit time +
penalty. Find the best variant of systems organization (with minimum average data acces
following options:
1. Block size = 32 words and Hit rate = 98% & SDRAM based main memory
2. Block size = 16 words and Hit rate = 96% & SDRAM based main memory
3. Block size = 32 words and Hit rate = 98% & DDR-SDRAM based main memory
4. Block size = 16 words and Hit rate = 96% & DDR-SDRAM based main memory
Calculate the value for the average data access time for each option. Fill in the Table 1.1
variant with min{Tav }.
For this question, we are already given the formula for average access time, which is:
Tav = (Rhit ⋅ Thit ) + (Rmiss ⋅ Tmiss )
The miss rate is given by Rmiss = 1 − Rhit .
Tav = (Rhit ⋅ Thit ) + ((1 − Rhit ) ⋅ Tmiss )
We already know how to calculate Tmiss from the previous question, which is:
Tmiss = Tbr + Thit
Substituting the formula for block replacement Tbr and block transfer Tbt :
• For SDRAM based main memory:
Tmiss = (Taddr + # of words × tbus ) (2) + Thit
• For DDR-SDRAM based main memory:
# of words × tbus
Tmiss = (Taddr + ) (2) + Thit
2
Using the formula for:
• Option 1
Tmiss = (80 ns + (32 words × 7.5 ns)) (2) + 10 ns = 650 ns
The following partial specifications are given:
Question 1.1
To determine the miss penalty (time to replace the block in cache) for the worst-case sce
block to be replaced always = 1) calculate the following:
• Bus clock period
• Bus transfer time
• Block replacement time (if D-bit = 1)
• Miss penalty
This question is just a matter of knowing the formula.
• The bus clock period is the reciprocal of the bus clock frequency.
1 1
tbus = = 6
≈ 7.5 × 10−9 s or 7.5 ns
fbus 133.33 × 10 Hz
Make sure you know the SI conversions, most notably for mega (M) and nano (n), as these will be those yo
tests.
• The block transfer time is the product of the number of words being transferred and the bus clock period.
Tbt = # of words × tbus = 32 words × 7.5 ns = 240 ns
• The block replacement time is given by the following formula.
, This is because it allows two data-words during one clock cycle period, so the block transfer gets cut in half. The r
the same.
Tmiss = Tbr = (80 ns + 120 ns)(2) + 10 ns = 410 ns
The system with DDR-SDRAM main memory has a miss penalty of 410 ns.
Question 1.3
Taking in account that average access time for the cache is equal to: Hit rate × Hit time +
penalty. Find the best variant of systems organization (with minimum average data acces
following options:
1. Block size = 32 words and Hit rate = 98% & SDRAM based main memory
2. Block size = 16 words and Hit rate = 96% & SDRAM based main memory
3. Block size = 32 words and Hit rate = 98% & DDR-SDRAM based main memory
4. Block size = 16 words and Hit rate = 96% & DDR-SDRAM based main memory
Calculate the value for the average data access time for each option. Fill in the Table 1.1
variant with min{Tav }.
For this question, we are already given the formula for average access time, which is:
Tav = (Rhit ⋅ Thit ) + (Rmiss ⋅ Tmiss )
The miss rate is given by Rmiss = 1 − Rhit .
Tav = (Rhit ⋅ Thit ) + ((1 − Rhit ) ⋅ Tmiss )
We already know how to calculate Tmiss from the previous question, which is:
Tmiss = Tbr + Thit
Substituting the formula for block replacement Tbr and block transfer Tbt :
• For SDRAM based main memory:
Tmiss = (Taddr + # of words × tbus ) (2) + Thit
• For DDR-SDRAM based main memory:
# of words × tbus
Tmiss = (Taddr + ) (2) + Thit
2
Using the formula for:
• Option 1
Tmiss = (80 ns + (32 words × 7.5 ns)) (2) + 10 ns = 650 ns
