DSY1501
ASSIGNMENT 1 2025
UNIQUE NO.
DUE DATE: 2025
, Question 1 [12 Marks]
1.1
In a negative-logic pulse, the trailing edge is the...
✅ d) falling edge
Explanation:
In digital electronics, negative logic interprets a high voltage as a logical '0' and a low
voltage as a logical '1'. In this context, the trailing edge of a pulse occurs when the
signal transitions from high to low. This drop is known as the falling edge, which
signifies the end of the pulse in negative logic systems.
1.2
A square wave has an ‘on’ time of 10 ms and an ‘off’ time of 50 ms. What is the
percentage duty cycle?
✅ a) 16.66%
Calculation:
Duty Cycle (%) = TonTon+Toff×100\frac{T_{on}}{T_{on} + T_{off}} \times 100Ton+Toff
Ton×100
= 1010+50×100=1060×100=16.66%\frac{10}{10 + 50} \times 100 = \frac{10}{60} \times
100 = 16.66\%10+5010×100=6010×100=16.66%
Explanation:
The duty cycle represents the percentage of one full cycle in which the signal remains
'on'. A 10 ms on-time within a 60 ms total cycle duration results in a 16.66% duty cycle.
1.3
ASSIGNMENT 1 2025
UNIQUE NO.
DUE DATE: 2025
, Question 1 [12 Marks]
1.1
In a negative-logic pulse, the trailing edge is the...
✅ d) falling edge
Explanation:
In digital electronics, negative logic interprets a high voltage as a logical '0' and a low
voltage as a logical '1'. In this context, the trailing edge of a pulse occurs when the
signal transitions from high to low. This drop is known as the falling edge, which
signifies the end of the pulse in negative logic systems.
1.2
A square wave has an ‘on’ time of 10 ms and an ‘off’ time of 50 ms. What is the
percentage duty cycle?
✅ a) 16.66%
Calculation:
Duty Cycle (%) = TonTon+Toff×100\frac{T_{on}}{T_{on} + T_{off}} \times 100Ton+Toff
Ton×100
= 1010+50×100=1060×100=16.66%\frac{10}{10 + 50} \times 100 = \frac{10}{60} \times
100 = 16.66\%10+5010×100=6010×100=16.66%
Explanation:
The duty cycle represents the percentage of one full cycle in which the signal remains
'on'. A 10 ms on-time within a 60 ms total cycle duration results in a 16.66% duty cycle.
1.3
