COS3721 ASSIGNMENT 1 SOLUTIONS 2023
QUESTION 1
1.1 Direct memory access is used for high-speed I/O devices in order to avoid increasing the
CPU’s execution load.
a. How does the CPU interface with the device to coordinate the transfer? (2)
To initiate a DMA transfer, the CPU first sets up the DMA registers, which contain a pointer
to the source of a transfer, a pointer to the destination of the transfer, and a counter of the
number of bytes to be transferred. Then the DMA controller proceeds to place addresses on
the bus to perform transfers, while the CPU is available to accomplish other work.
b. How does the CPU know when the memory operations are complete? (2)
When the device is finished with its operation, it interrupts the CPU to indicate the
completion of the operation. Both the device and the CPU can be accessing memory
simultaneously. The memory controller provides access to the memory bus in a fair manner
to these two entities.
c. The CPU is allowed to execute other programs while the DMA controller is
transferring
data. Does this process interfere with the execution of the user programs? If so, describe
what forms of interference are caused?(4)
Both the CPU and the DMA controller are bus masters. A problem would be created if both
the CPU and the DMA controller want to access the memory at the same time. Accordingly,
the CPU should be momentarily prevented from accessing main memory when the DMA
QUESTION 1
1.1 Direct memory access is used for high-speed I/O devices in order to avoid increasing the
CPU’s execution load.
a. How does the CPU interface with the device to coordinate the transfer? (2)
To initiate a DMA transfer, the CPU first sets up the DMA registers, which contain a pointer
to the source of a transfer, a pointer to the destination of the transfer, and a counter of the
number of bytes to be transferred. Then the DMA controller proceeds to place addresses on
the bus to perform transfers, while the CPU is available to accomplish other work.
b. How does the CPU know when the memory operations are complete? (2)
When the device is finished with its operation, it interrupts the CPU to indicate the
completion of the operation. Both the device and the CPU can be accessing memory
simultaneously. The memory controller provides access to the memory bus in a fair manner
to these two entities.
c. The CPU is allowed to execute other programs while the DMA controller is
transferring
data. Does this process interfere with the execution of the user programs? If so, describe
what forms of interference are caused?(4)
Both the CPU and the DMA controller are bus masters. A problem would be created if both
the CPU and the DMA controller want to access the memory at the same time. Accordingly,
the CPU should be momentarily prevented from accessing main memory when the DMA
