Eachregisterfield is 5bits
Opcodes are 7 bits 6
bib
Some instructionsare 32bitsothers31
Watchoutfor immediatefields
Topic V05
Binary Representation
of Instructions
1
, Representing Instructions
Instructions are encoded in a binary representation
Called machine code
RISC-V instructions
Encoded as 32-bit instruction words
Small number of formats encoding operation code (opcode),
register number, …
Regularity!
Register Names:
t0 – t2 ⟺ x5 – x7 This was a choice by hardware
t3 – t6 ⟺ x28 – x31 designer
s0 – s1 ⟺ x8 – x9 You must know these
s2 – s11c⟺ x18 – x27
S2 SII 2 18 X27
2
, bit field each rectangle
Representing Instructions: R-Type
x5 x23 x21
add t0, s7, s5
func7 rs2 rs1 func3 rd op
0x00 21 23 0xO 5 0x33
0 1
e 3 0
es 3
es
31 25 24 20 19 15 14 12 11 7 6 0
000000O 1010 1 10111 00O 00101 0110011
Bto
0 1 IET 18T I0
In memory we would see: 0x015B82B3
1B BET1 3
Each register fieldhas
0x01
0x015
0x0
5bits becausethereare
op: Opcode to specify the operation and format of an instruction zaregisters andsoyouneed
rd: register destination operand 5bits torepresentanregisters
funct3: co
function code; partially, specifies the variant of the instruction to be si
executed
rs1: first register source operand Tassinari
O
rs2:
funct7:
second register source operand
function code specifies the variant of the instruction to be executed
Hipaa
3
Opcodes are 7 bits 6
bib
Some instructionsare 32bitsothers31
Watchoutfor immediatefields
Topic V05
Binary Representation
of Instructions
1
, Representing Instructions
Instructions are encoded in a binary representation
Called machine code
RISC-V instructions
Encoded as 32-bit instruction words
Small number of formats encoding operation code (opcode),
register number, …
Regularity!
Register Names:
t0 – t2 ⟺ x5 – x7 This was a choice by hardware
t3 – t6 ⟺ x28 – x31 designer
s0 – s1 ⟺ x8 – x9 You must know these
s2 – s11c⟺ x18 – x27
S2 SII 2 18 X27
2
, bit field each rectangle
Representing Instructions: R-Type
x5 x23 x21
add t0, s7, s5
func7 rs2 rs1 func3 rd op
0x00 21 23 0xO 5 0x33
0 1
e 3 0
es 3
es
31 25 24 20 19 15 14 12 11 7 6 0
000000O 1010 1 10111 00O 00101 0110011
Bto
0 1 IET 18T I0
In memory we would see: 0x015B82B3
1B BET1 3
Each register fieldhas
0x01
0x015
0x0
5bits becausethereare
op: Opcode to specify the operation and format of an instruction zaregisters andsoyouneed
rd: register destination operand 5bits torepresentanregisters
funct3: co
function code; partially, specifies the variant of the instruction to be si
executed
rs1: first register source operand Tassinari
O
rs2:
funct7:
second register source operand
function code specifies the variant of the instruction to be executed
Hipaa
3
