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EEE 334 – Online Experiment 5: Single Stage MOS Amplifiers (2025/26 Update) – Complete A+ Lab Report and LTspice Simulation Guide

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This detailed report covers EEE 334 Online Experiment 5: Single Stage MOS Amplifiers, focusing on NMOS-based common-source, common-gate, and common-drain amplifier configurations. It includes full circuit construction steps, LTspice simulation setup, waveform screenshots, gain and frequency response calculations, and detailed error analysis. The document also provides complete data, discussion, and post-lab questions aligned with the 2025/26 EEE 334 curriculum—ideal for lab preparation, report writing, and practical understanding of MOS amplifier behavior.

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EEE 334:
Online Experiment 5 Single Stage MOS Amplifiers

Experiment 2025/26 Update, 100% Guaranteed Pass

||Complete A+ Guide



This Document Contains:

 EEE 334

 Online Experiment 5 Single Stage MOS Amplifiers Experiment

 100% Guaranteed Pass

 Complete A+ Guide

,Introduction:

- What is this experiment about?

This experiment is to learn about single stage MOS amplifiers. We will be using the
NMOS transistor to test three different single stage amplifiers such as common-source,
common-gate, and common-drain amplifiers.

- What components or special equipment will be used?

Resistors, wires, breadboard, Analog discovery unit, and a multimeter. Also,
Waveform and LTspice.




Equipment and Components:

a. Equipment

Name Model Quantity
ADK Unit 2
ADK kit




b. Components


Name Value Quantity
Resistors 2.2KΩ, 1.5KΩ, 200KΩ, 68KΩ 1 Each
Capacitor 1uF, 4.7uF 2 Each
MOS CD4007 1


Course of Action:

5.1 DC biasing of an NMOS transistor
1. We start by building the circuit showing in Fig. 5.3. we need to connect pin 7 to the
source node. Also, we need to place 1 uf capacitor between pin 14 and ground. RG2 =



1

, 200KOhms, RG1 = 68KOhms, RS = 1.5KOhms and, RD = 2.2KOhms. Set VDD to 5V and
make sure that Vds is around 2-2.5.
2. We need to measure and record VRD and VRS
3. Also, we need to calculate ID and IS.
4. Remove the power from the circuit.
5. Stimulate the circuit in LTspice. Make sure to set the NMOS model parameters as in
Lab 4, section 4.4
6. Screen shot schematic and plot and attach them to the answer sheet.
7. Do a % error to compare the lab and LTspice results.


5.2 Common-Source (CS) amplifier

1. We need to modify the circuit by adding CC1 = 1uF, CC2, and CS both 4.7uF as shown
in fig. 5.4
2. RL is internal resistance of the oscilloscope it is about 1 MOhms. Rsig represent the
resistance of the function generation and it is about 50Ohms. Do not place them on
board.
3. Turn on the DC supply
4. Set the function generator to 100mVpp and 10 kHz frequency, then connect it to the
circuit. Set the offset to 0V.
5. Using the oscilloscope obtain the waveform of VS and VO. and determine the phase
shift of VS with respect to VO. Take a screenshot and calculate the gain of the CS
amplifier.
6. Remove the power from the source
7. Stimulate in LTspice use VOFF=0, AC=1, VAMPL=0.05, FREQ=10k for the AC and
transient signal source. Place 1Meg for RL and 50 for Rsig. finally set the NMOS model
parameters as in Lab 4, section 4.4.
8. For transient analysis obtain the waveform of Vs and VO. and calculate the gain of CS
amplifier from the calculated results.
9. For the AC Analysis obtain the frequency response for Vo/VS in dB. And determine
the maximum gain(dB), fL, fH, and BW.
10. Screen shot the plot and attach it to the result sheets
11. Use %error to compare the lab and the LTspice results.



5.3 Common-Gate (CG) amplifier

1. We need to modify the circuit by adding CC1 and CC2 both = 4.7uF, and CS = 1uF as
shown in fig. 5.5
2. RL is internal resistance of the oscilloscope it is about 1 MOhms. Rsig represent the
resistance of the function generation and it is about 50Ohms. Do not place them on
board.
3. Turn on the DC supply


2

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