100% satisfaction guarantee Immediately available after payment Read online or as PDF No strings attached 4.6 TrustPilot
logo-home
Other

CISM 3330 EXAM 1 STUDY GUIDE

Rating
-
Sold
-
Pages
8
Uploaded on
11-03-2025
Written in
2024/2025

CISM 3330 EXAM 1 STUDY GUIDE

Institution
CISA 3330
Course
CISA 3330

Content preview

CISM 3330 EXAM 1 STUDY GUIDE
Bitwise Operators - Answers :& - (AND) copies a bit to the result if it exists in both
operands:
0011 1100 & 0000 1101 = 0000 1100

| - (OR) copies a bit if it exists in either operand:
0011 1100 | 0000 1101 = 0011 1101

^ - (XOR) copies the bit if it is set in one operand but not both:
0011 1100 ^ 0000 1101

~ - 'flips' bits:
~0011 1100 = 1100 0011

<< - left shift:
0011 1100 << 2 = 1111 0000

>> - right shift:
0011 1100 >> 2 = 0000 1111

File Compilation - Answers :Compilation:
c code translated into assembly (hello.s)
actual data is referenced here
text and data sections

Assemble:
Assembly code translated into machine code
object file (hello.o)
uses placeholders for memory addresses that need to be used
relocations - list of placeholders
symbol table - where the function is

Link:
Combine with other .o files
places all text/data parts in memory, then writes info into executable
gets code from libraries

Pointer arithmetic - Answers :char *hello = "Hello World";
hello + 1 ' 'e'
*(hello + 1) = 'e'
hello[1] = 'e'

Stack v Heap - Answers :Stack: stored memory from local variables (life of the function),
grows down
Heap: new and malloc, dynamic

, ATT Syntax - Answers :destination last
'( )' means in memory
'$' means constant
plain number/label means value in memory

movq $42, (%rbx) = memory[rbx] <- 42`

LEA - Answers :Load Effective adress
skips memory access, just uses memory
leaq 4(%rax), %rax = addq 4, %rax

Condition Codes - Answers :set by almost all arithmetic instructions (addq, subq, etc)

Store info on last arithmetic result

jg, jle: jump greater than, jump less than
based on the result of subtraction
0: equal, positive: greater than, negative: less than

RISC v CISA - Answers :RISC:
fewer, simpler instructions
separate instructions to access memory
fixed length instructions
more registers
no "loops" in single instructions
no instructions with 2 memory operands
few addressing modes
RISC makes simpler hardware

ISA Choices - Answers :condition codes
addressing modes
number of operands
instruction complexity

Which op codes do arithmetic? - Answers :rm, mr, pop, push, call. ret, op

how to declare typedef/struct - Answers :typedef stuct foo {
int x;
} bar;

Legal:
bar x;
struct foo x;

sub - Answers :sub rax, rbx

Written for

Institution
CISA 3330
Course
CISA 3330

Document information

Uploaded on
March 11, 2025
Number of pages
8
Written in
2024/2025
Type
OTHER
Person
Unknown

Subjects

Get to know the seller

Seller avatar
Reputation scores are based on the amount of documents a seller has sold for a fee and the reviews they have received for those documents. There are three levels: Bronze, Silver and Gold. The better the reputation, the more your can rely on the quality of the sellers work.
GEEKA YALA UNIVERSITY
Follow You need to be logged in order to follow users or courses
Sold
2055
Member since
4 year
Number of followers
1446
Documents
51275
Last sold
8 hours ago

3.8

353 reviews

5
177
4
61
3
46
2
16
1
53

Recently viewed by you

Why students choose Stuvia

Created by fellow students, verified by reviews

Quality you can trust: written by students who passed their tests and reviewed by others who've used these notes.

Didn't get what you expected? Choose another document

No worries! You can instantly pick a different document that better fits what you're looking for.

Pay as you like, start learning right away

No subscription, no commitments. Pay the way you're used to via credit card and download your PDF document instantly.

Student with book image

“Bought, downloaded, and aced it. It really can be that simple.”

Alisha Student

Frequently asked questions