Ecen 350 post-Exam1/pre-Exam2
quizzes well answered
For all R-Type instruction, Read Data 2 is connected to the ALU.
(quiz 11, true or false) - ANS ✔true
EXPLANATION:
In the LDUR and STUR instructions, the ALU is used for the __________ calculation.
(quiz 11, fill in the blank) - ANS ✔address
EXPLANATION:
The registerfile does not produce any output on Read Data 1 and Read Data 2 for the B
instruction.
(quiz 11, true or false) - ANS ✔false
EXPLANATION:
Assuming Fetch has placed an instruction on the bus called I[31:0] (in Verilog notation), which
wires should be connected to "Read Addr 2" on the register file for the proper execution of R-
Type instructions.
,(quiz 11, fill in the blank) - ANS ✔I[20:16]
EXPLANATION:
For the CBZ instruction, the ALU must be set to perform the "pass _________" operation.
(quiz 11, fill in the blank) - ANS ✔input b
EXPLANATION:
A given program has the following instruction mix:
Instruction Type | Frequency
R-type | 35%
LDUR | 34%
STUR | 14%
CBZ | 15%
B | 2%
The fraction of all instructions that use the instruction memory is: _____
The fraction of all instructions that use the register file is: _____
The fraction of all instructions that use the sign-extend unit is: _____
The fraction of all instructions that use the ALU is: _____
The fraction of all instructions that use the data memory is: _____
Enter you answers in percent.
(quiz 11, fill in FIVE blanks) - ANS ✔100%
98% (everything but B)
,65% (everything but R-type)
98% (everything but B)
48% (LDUR+STUR only)
EXPLANATION:
Consider an ISA with a sign-extender unit that accepts an 8-bit branch instruction of the
following format
opcode | offset | opcode
2 bits | 4 bits | 2 bits
and outputs an 8-bit sign-extended offset.
Let the input bits be X7, X6, ..., X0 and the output bits be Y7, Y6, ..., Y0.
Enter the value of each output Yi in terms of an input Xj. (Note: X0 and Y0 are the rightmost,
least-significant bits.)
Y0 = _____
Y1 = _____
Y2 = _____
Y3 = _____
Y4 = _____
Y5 = _____
Y6 = _____
Y7 = _____
(quiz 11, fill in EIGHT blanks) - ANS ✔X2
X3
, X4
X5
X5
X5
X5
X5
EXPLANATION:
With the previous question as warmup, consider now a different ISA, in which the sign-extender
must consider two types of branch instruction formats:
Conditional branch:
opcode | offset | opcode
1 bits | 5 bits | 2 bits
Unconditional branch:
opcode | offset
1 bits | 7 bits
Let the input bits be X7, X6, ..., X0 and the output bits be Y7, Y6, ..., Y0, as before.
The bit in the first opcode (X7) encodes the instruction format. If X7 = 0, it's a conditional
branch, while if X7 = 1, it's an unconditional one.
Complete the logic for each output Yi in terms of inputs Xj below. Enter answers in the format
"X0 AND X1" or "X0 AND NOT(X1)".
quizzes well answered
For all R-Type instruction, Read Data 2 is connected to the ALU.
(quiz 11, true or false) - ANS ✔true
EXPLANATION:
In the LDUR and STUR instructions, the ALU is used for the __________ calculation.
(quiz 11, fill in the blank) - ANS ✔address
EXPLANATION:
The registerfile does not produce any output on Read Data 1 and Read Data 2 for the B
instruction.
(quiz 11, true or false) - ANS ✔false
EXPLANATION:
Assuming Fetch has placed an instruction on the bus called I[31:0] (in Verilog notation), which
wires should be connected to "Read Addr 2" on the register file for the proper execution of R-
Type instructions.
,(quiz 11, fill in the blank) - ANS ✔I[20:16]
EXPLANATION:
For the CBZ instruction, the ALU must be set to perform the "pass _________" operation.
(quiz 11, fill in the blank) - ANS ✔input b
EXPLANATION:
A given program has the following instruction mix:
Instruction Type | Frequency
R-type | 35%
LDUR | 34%
STUR | 14%
CBZ | 15%
B | 2%
The fraction of all instructions that use the instruction memory is: _____
The fraction of all instructions that use the register file is: _____
The fraction of all instructions that use the sign-extend unit is: _____
The fraction of all instructions that use the ALU is: _____
The fraction of all instructions that use the data memory is: _____
Enter you answers in percent.
(quiz 11, fill in FIVE blanks) - ANS ✔100%
98% (everything but B)
,65% (everything but R-type)
98% (everything but B)
48% (LDUR+STUR only)
EXPLANATION:
Consider an ISA with a sign-extender unit that accepts an 8-bit branch instruction of the
following format
opcode | offset | opcode
2 bits | 4 bits | 2 bits
and outputs an 8-bit sign-extended offset.
Let the input bits be X7, X6, ..., X0 and the output bits be Y7, Y6, ..., Y0.
Enter the value of each output Yi in terms of an input Xj. (Note: X0 and Y0 are the rightmost,
least-significant bits.)
Y0 = _____
Y1 = _____
Y2 = _____
Y3 = _____
Y4 = _____
Y5 = _____
Y6 = _____
Y7 = _____
(quiz 11, fill in EIGHT blanks) - ANS ✔X2
X3
, X4
X5
X5
X5
X5
X5
EXPLANATION:
With the previous question as warmup, consider now a different ISA, in which the sign-extender
must consider two types of branch instruction formats:
Conditional branch:
opcode | offset | opcode
1 bits | 5 bits | 2 bits
Unconditional branch:
opcode | offset
1 bits | 7 bits
Let the input bits be X7, X6, ..., X0 and the output bits be Y7, Y6, ..., Y0, as before.
The bit in the first opcode (X7) encodes the instruction format. If X7 = 0, it's a conditional
branch, while if X7 = 1, it's an unconditional one.
Complete the logic for each output Yi in terms of inputs Xj below. Enter answers in the format
"X0 AND X1" or "X0 AND NOT(X1)".
