COSC 290 FINAL EXAM questions well answered to pass

COSC 290 FINAL EXAM questions well
answered to pass

One of MARIE's 7 registers: Accumulator (AC) - correct answer ✔✔a 16 bit register that holds a
conditional operator

(e.g. "less than") or one operand of a two-operand instruction



How can the exact sequence of microoperations that are carried out by an instruction be specified? -
correct answer ✔✔By using register transfer language (RTL)

-In the MARIE RTL we use the notation M[X] to indicate the actual data value stored in memory location
X, and <- to indicate the transfer of bytes to a register or memory location



The RTL for the LOAD instruction is: - correct answer ✔✔MAR <- X

MBR <- M[MAR]

AC <- MBR



The RTL for the ADD instruction is: - correct answer ✔✔MAR <- X

MBR <- M[MAR]

AC <- AC+MBR



Recall that SKIPCOND skips the next instruction according to the value of the AC

-The RTL for this instruction is the most complex in our instruction set - correct answer ✔✔If IR[11-10] =
00 then

-----If AC < 0 then PC <- PC + 1

else if IR[11-10] = 01 then

-----if AC = 0 then PC <- PC + 1

else if IR[11-10] = 11 then

-----if AC > 0 then PC <- PC + 1

,3 Indirect Addressing Mode Instructions in the MARIE Instruction Set - correct answer ✔✔LOADI X,
STOREI X, ADDI X



LOADI X in RTL (indirect addressing mode) - correct answer ✔✔MAR <- X

MBR <- M[MAR]

MAR <- MBR

MBR <- M[MAR]

AC <- MBR



STOREI X in RTL (indirect addressing mode) - correct answer ✔✔MAR <- X

MBR <- M[MAR]

MAR <- MBR

MBR <- AC

M[MAR] <- MBR



The ADDI instruction is a combination of LOADI X & ADD X (indirect addressing mode)



ADDI X in RTL: - correct answer ✔✔MAR <- X

MBR <- M[MAR]

MAR <-MBR

MBR <- M[MAR]

AC <- AC + MBR



The Jump-and-Store instruction, JNS, gives us limited subroutine functionality



JNS in RTL: - correct answer ✔✔MBR <- PC

MAR <- X

M[MAR] <- MBR

MBR <-X

, AC <- 1

AC <- AC + MBR

AC <- PC



CLEAR in RTL: - correct answer ✔✔AC <- 0

-all it does is set the contents of the accumulator to all zeroes



Computer memory consists of a linear array of addressable storage cells that are similar to registers -
correct answer ✔✔Memory can be byte addressable, or word addressable, where a word typically
consists of two or more bytes.



Memory constructed of RAM chips, referred to in terms of LxW (length x width) - correct answer ✔✔if
the memory word size of the machine is 16bits, then a 4M x 16 RAM chip gives us 4 mB of 16 bit
memory locations



A single shared memory module causes sequentialization of access. Memory interleaving, which splits
memory across multiple memory modules (or banks), can be used to help relieve this. - correct answer
✔✔-----With low-order interleaving, the low order bits of the address are used to select the bank



-----Accordingly, in high-order interleaving, the high order address bits specify the memory bank



High-order interleaving, the more intuitive organization, distributes the addresses so that each module
contains consecutive addresses.



Low-order interleaved memory places consecutive words of memory in different memory modules. With
the appropriate buses using low-order interleaving, a read or write using one module can be started
before a read or write using another module actually completes.



Example of memory consisting of 16 2K x 8 bit chips - correct answer ✔✔Row 0 |2Kx8| -Memory is 32K
= 2^5 x 2^10 = 2^15

Row 1 |2Kx8| -15 bits needed for each address

|.........| -need 4 bits to select the chip & 11 bits for offset into the the chip that selects the byte