AS/A Unit 1 | SLR 1
Structure and function o
Typical examination questions Specification and learning objectiv
AS Level A Level Specification point description
1. Describe the stages of the fetch-decode-execute cycle. [4]
The arithmetic logic unit; ALU
1.1.1a 1.1.1a Accumulator; ACC, Memory
Fetch is the first step in the FDE cycle. It involves the program counter being incremented; the Current Instruction Register;
contents copied to the MAR. Then, a read signal is sent from the CU to the address bus. This assembly language program.
allows the location in memory to be copied into the MDR.
1.1.1b 1.1.1b The fetch-decode-execute cy
Next is the decode step. This involves the contents form the MDR being copied to the CIR, and
the instruction is decoded via a lookup table in the decode unit. 1.1.1c 1.1.1c The factors affecting the perf
Finally, the execute step is when the opcode and operand are used to say what will happen 1.1.1d The use of pipelining in a pro
next. If it was decoded to ADD the value in memory location 6, then 6 would be copied to the
MAR and then the value in location 6 would be copied to the MDR and used in an addition in 1.1.1d 1.1.1e Von Neumann, Harvard and
the ALU.
Minimum expectations and learnin
Terms 1-21 from A Level Key Terminology sh
2. Increasing the number of cores affects the performance of the CPU. Explain why this increase
in performance is not linear. [2]
You must include an illustration that depict
the connection between the registers, direc
Because code can’t always take advantage of the extra core. I.e., if google chrome tabs used
different cores, then it could take advantage, but if a core was waiting on an answer from an You must show how an assembly language
BRANCH affects the contents of the register
instruction set being decoded by the other core, then it might take longer to do the same thing.
Therefore, the increase is not linear as it depends on which programs are being run and how
they have been coded. You must describe how several factors affec
You must explain how pipelining improves t
You must illustrate the difference between
3. State the purpose of the address bus. [1]
Answer the exam questions.
The value in the MAR is sent down the address bus to fetch the item needed.
Resources
4. Name one register other than the PC found in the CPU and describe its purpose. [2] PG Online textbook page ref: 1-12
Craig ‘n’ Dave videos for SLR 1
The mdr
Feedback
Structure and function o
Typical examination questions Specification and learning objectiv
AS Level A Level Specification point description
1. Describe the stages of the fetch-decode-execute cycle. [4]
The arithmetic logic unit; ALU
1.1.1a 1.1.1a Accumulator; ACC, Memory
Fetch is the first step in the FDE cycle. It involves the program counter being incremented; the Current Instruction Register;
contents copied to the MAR. Then, a read signal is sent from the CU to the address bus. This assembly language program.
allows the location in memory to be copied into the MDR.
1.1.1b 1.1.1b The fetch-decode-execute cy
Next is the decode step. This involves the contents form the MDR being copied to the CIR, and
the instruction is decoded via a lookup table in the decode unit. 1.1.1c 1.1.1c The factors affecting the perf
Finally, the execute step is when the opcode and operand are used to say what will happen 1.1.1d The use of pipelining in a pro
next. If it was decoded to ADD the value in memory location 6, then 6 would be copied to the
MAR and then the value in location 6 would be copied to the MDR and used in an addition in 1.1.1d 1.1.1e Von Neumann, Harvard and
the ALU.
Minimum expectations and learnin
Terms 1-21 from A Level Key Terminology sh
2. Increasing the number of cores affects the performance of the CPU. Explain why this increase
in performance is not linear. [2]
You must include an illustration that depict
the connection between the registers, direc
Because code can’t always take advantage of the extra core. I.e., if google chrome tabs used
different cores, then it could take advantage, but if a core was waiting on an answer from an You must show how an assembly language
BRANCH affects the contents of the register
instruction set being decoded by the other core, then it might take longer to do the same thing.
Therefore, the increase is not linear as it depends on which programs are being run and how
they have been coded. You must describe how several factors affec
You must explain how pipelining improves t
You must illustrate the difference between
3. State the purpose of the address bus. [1]
Answer the exam questions.
The value in the MAR is sent down the address bus to fetch the item needed.
Resources
4. Name one register other than the PC found in the CPU and describe its purpose. [2] PG Online textbook page ref: 1-12
Craig ‘n’ Dave videos for SLR 1
The mdr
Feedback
