®
Registers
Buffer Register
Controlled Buffer Register
Shift Registers
Serial In Serial Out (SISO)
Shift Left Mode
Shift Right Mode
Serial In Parallel Out (SIPO)
Parallel In Serial Out
Parallel In Parallel Out
Bidirectional Shift Registers
Serial Load
Parallel Load
Universal Shift Register
Applications
Buffer Register
Controlled Buffer Register
Used to control input and output of the register by connecting tri-state devices at the input and output sides of the register.
For storage, ˉ /WˉR → LOW
LOAD
ˉ → LOW
For output, RD
Shift Registers
Registers 1
, Serial In Serial Out (SISO)
Shift Left Mode
CP Q_3 Q_2 Q_1 Q_0 D_in
Initially 0 0 0 0 1
↓ (1st) 0 0 0 1 1
↓ (2nd) 0 0 1 1 1
↓ (3rd) 0 1 1 1 1
↓ (4th) 1 1 1 1 1
Shift Right Mode
CP D_in Q_3 Q_2 Q_1 Q_0
Initially 1 0 0 0 0
↓ (1st) 1 1 0 0 0
↓ (2nd) 1 1 1 0 0
↓ (3rd) 1 1 1 1 0
↓ (4th) 1 1 1 1 1
Serial In Parallel Out (SIPO)
CP D_in Q_3 Q_2 Q_1 Q_0
Initially 1 0 0 0 0
↓ (1st) 1 1 0 0 0
Registers 2
Registers
Buffer Register
Controlled Buffer Register
Shift Registers
Serial In Serial Out (SISO)
Shift Left Mode
Shift Right Mode
Serial In Parallel Out (SIPO)
Parallel In Serial Out
Parallel In Parallel Out
Bidirectional Shift Registers
Serial Load
Parallel Load
Universal Shift Register
Applications
Buffer Register
Controlled Buffer Register
Used to control input and output of the register by connecting tri-state devices at the input and output sides of the register.
For storage, ˉ /WˉR → LOW
LOAD
ˉ → LOW
For output, RD
Shift Registers
Registers 1
, Serial In Serial Out (SISO)
Shift Left Mode
CP Q_3 Q_2 Q_1 Q_0 D_in
Initially 0 0 0 0 1
↓ (1st) 0 0 0 1 1
↓ (2nd) 0 0 1 1 1
↓ (3rd) 0 1 1 1 1
↓ (4th) 1 1 1 1 1
Shift Right Mode
CP D_in Q_3 Q_2 Q_1 Q_0
Initially 1 0 0 0 0
↓ (1st) 1 1 0 0 0
↓ (2nd) 1 1 1 0 0
↓ (3rd) 1 1 1 1 0
↓ (4th) 1 1 1 1 1
Serial In Parallel Out (SIPO)
CP D_in Q_3 Q_2 Q_1 Q_0
Initially 1 0 0 0 0
↓ (1st) 1 1 0 0 0
Registers 2