ARM Accredited SoC Specialist AASoCS Practice Exam
**Question 1.** Which ARM architecture introduced the A64 (64‑bit) instruction
set?
A) Armv7‑A
B) Armv8‑A
C) Armv9‑A
D) Armv6‑M
Answer: B
Explanation: Armv8‑A added the A64 instruction set, providing native 64‑bit
execution while retaining A32/T32 for backward compatibility.
**Question 2.** In the Cortex‑A family, which core is primarily designed for
high‑performance, out‑of‑order execution?
A) Cortex‑A53
B) Cortex‑A72
C) Cortex‑A5
D) Cortex‑A7
Answer: B
Explanation: The Cortex‑A72 is a high‑performance, out‑of‑order core, whereas
the A53 is an in‑order, power‑efficient design.
**Question 3.** Which execution state uses the 32‑bit ARM (A32) instruction set?
A) AArch64
B) AArch32
, ARM Accredited SoC Specialist AASoCS Practice Exam
C) EL3 only
D) Secure State only
Answer: B
Explanation: AArch32 execution state runs the 32‑bit A32/T32 instruction sets;
AArch64 runs the 64‑bit A64 set.
**Question 4.** What is the primary purpose of the Generic Interrupt Controller
(GIC) in an ARM SoC?
A) Cache management
B) Memory translation
C) Interrupt distribution and prioritisation
D) Power gating
Answer: C
Explanation: The GIC collects, prioritises, and routes interrupts to the appropriate
CPU cores.
**Question 5.** Which of the following is a SIMD extension in ARM processors?
A) TrustZone
B) NEON
C) SVE
D) ARMv8‑M Mainline
Answer: B
, ARM Accredited SoC Specialist AASoCS Practice Exam
Explanation: NEON provides SIMD capabilities for multimedia and
signal‑processing workloads.
**Question 6.** In ARMv8‑A, which Exception Level has the highest privilege?
A) EL0
B) EL1
C) EL2
D) EL3
Answer: D
Explanation: EL3 (Secure Monitor) holds the highest privilege, used for secure
world entry/exit and monitor calls.
**Question 7.** Which memory attribute indicates that a region can be cached by
both inner and outer caches?
A) Shareable
B) Device
C) Outer‑Write‑Back, Inner‑Write‑Back
D) Non‑Cacheable
Answer: C
Explanation: Outer‑Write‑Back/Inner‑Write‑Back attributes enable caching at both
levels.
, ARM Accredited SoC Specialist AASoCS Practice Exam
**Question 8.** What does the DSB (Data Synchronisation Barrier) instruction
guarantee?
A) All previous instructions have completed execution before any following
instruction is fetched.
B) All explicit memory accesses before the DSB are globally observable before any
after it.
C) Only instruction ordering is enforced.
D) It flushes the TLB.
Answer: B
Explanation: DSB ensures that all explicit memory accesses before it are
completed and visible before subsequent accesses.
**Question 9.** Which AXI channel carries write address information?
A) W channel
B) AR channel
C) AW channel
D) B channel
Answer: C
Explanation: The AW (Address Write) channel transmits write address and control
signals.
**Question 10.** In an AMBA AXI‑Lite interface, how many data beats can be
transferred per transaction?
**Question 1.** Which ARM architecture introduced the A64 (64‑bit) instruction
set?
A) Armv7‑A
B) Armv8‑A
C) Armv9‑A
D) Armv6‑M
Answer: B
Explanation: Armv8‑A added the A64 instruction set, providing native 64‑bit
execution while retaining A32/T32 for backward compatibility.
**Question 2.** In the Cortex‑A family, which core is primarily designed for
high‑performance, out‑of‑order execution?
A) Cortex‑A53
B) Cortex‑A72
C) Cortex‑A5
D) Cortex‑A7
Answer: B
Explanation: The Cortex‑A72 is a high‑performance, out‑of‑order core, whereas
the A53 is an in‑order, power‑efficient design.
**Question 3.** Which execution state uses the 32‑bit ARM (A32) instruction set?
A) AArch64
B) AArch32
, ARM Accredited SoC Specialist AASoCS Practice Exam
C) EL3 only
D) Secure State only
Answer: B
Explanation: AArch32 execution state runs the 32‑bit A32/T32 instruction sets;
AArch64 runs the 64‑bit A64 set.
**Question 4.** What is the primary purpose of the Generic Interrupt Controller
(GIC) in an ARM SoC?
A) Cache management
B) Memory translation
C) Interrupt distribution and prioritisation
D) Power gating
Answer: C
Explanation: The GIC collects, prioritises, and routes interrupts to the appropriate
CPU cores.
**Question 5.** Which of the following is a SIMD extension in ARM processors?
A) TrustZone
B) NEON
C) SVE
D) ARMv8‑M Mainline
Answer: B
, ARM Accredited SoC Specialist AASoCS Practice Exam
Explanation: NEON provides SIMD capabilities for multimedia and
signal‑processing workloads.
**Question 6.** In ARMv8‑A, which Exception Level has the highest privilege?
A) EL0
B) EL1
C) EL2
D) EL3
Answer: D
Explanation: EL3 (Secure Monitor) holds the highest privilege, used for secure
world entry/exit and monitor calls.
**Question 7.** Which memory attribute indicates that a region can be cached by
both inner and outer caches?
A) Shareable
B) Device
C) Outer‑Write‑Back, Inner‑Write‑Back
D) Non‑Cacheable
Answer: C
Explanation: Outer‑Write‑Back/Inner‑Write‑Back attributes enable caching at both
levels.
, ARM Accredited SoC Specialist AASoCS Practice Exam
**Question 8.** What does the DSB (Data Synchronisation Barrier) instruction
guarantee?
A) All previous instructions have completed execution before any following
instruction is fetched.
B) All explicit memory accesses before the DSB are globally observable before any
after it.
C) Only instruction ordering is enforced.
D) It flushes the TLB.
Answer: B
Explanation: DSB ensures that all explicit memory accesses before it are
completed and visible before subsequent accesses.
**Question 9.** Which AXI channel carries write address information?
A) W channel
B) AR channel
C) AW channel
D) B channel
Answer: C
Explanation: The AW (Address Write) channel transmits write address and control
signals.
**Question 10.** In an AMBA AXI‑Lite interface, how many data beats can be
transferred per transaction?
