CNIT 176 Exam Study Guide | Latest and Verified
Direct Memory Access - Required conditions
-The I/O interface and memory must be connected
-The I/O controller must be capable of reading and writing to memory
-Conflicts between the CPu and the I/O controller must be avoided
-Interrupt required for completion
Basic Model of I/O
Processing speed or program execution
-Determined primarily by ability of I/O operations to stay ahead of processor
-Input --> Processor --> Output
I/O Requirements
1. Means for addressing different peripheral devices
2. A way for peripheral devices to initiate communication
with the CPU
3. An efficient means of transferring data directly between
I/O and memory for large data transfers since programmed I/O is suitable only for slow devices
and individual word transfers
4. Buses that interconnect high-speed I/O devices with the computer must support high data
transfer rates
5. Capability of handling devices operating at varying speeds with varying delays
6. Means for handling devices with extremely different control requirements
Peripherals
External devices what you connect to a computer (other than CPU, Power, memory)
Simple I/O configuration
CPU -> I/O Controller -> I/O device
,Northbridge
special chip to handle communication between CPU, GPU, and RAM
Southbridge
Special chip to handle communication between northbridge and interfaces such as the USB and
SATA (harddrive) interfaces
More Complex I/O Module, Intel Xeon
Separate IO controller chipes might have been present for Ethernet, Audio, if not part of
Southbridge
In the Intel Core Series
Northbridge is now a part of the CPU
Advanced I/O techniques - Programmed I/O
-CPU controlled I/O and CPU initiated
-I/O data and address registers in CPU
-one word transfer per I/O instruction
-Address information for each I/O device
-Full instruction fetch/execute cycle
--Used or keyboard and other communication with I/O controllers
Advanced I/O techniques - Interrupt Driven I/O
-External input controls
-CPU adopts whatever it wants
-Not CPU initiated
Advanced I/O techniques - Direct Memory Access Controllers
Method for transferring data between main memory and a device that bypasses the CPU
Programmed I/O example
,see docs
Accumulator
where the CPU does its scratch work, in the ALU
Interrupts in the CPU
-Signal that causes the CPU to alter its normal flow of instruction execution
-Frees CPU from waiting for events
-Provides control for external I/O initiation
Interrupts in the CPU - examples
-Unexpected input
-Abnormal situation
-Illegal situations
-Multitasking, multiprocessing
Interrupt Teminology - Interrupt lines
Hardware on one mor more special control lines to the CPU
Interrupt Terminology - Interrupt request
see docs
Interrupt Terminology - Interrupt handlers
-Program that services the interrupt
-Also known as an interrupt routine or device driver
Interrupt Terminology - Context
-Saved registers of a program before control is transferred to the interrupt handler
-Allows program to resume exactly where it left over when control returns to interrupted
program
Use of Interrupts
, Notify that an external event has occurred
- Real or time sensitive
Signal Completion
-Printer ready or buffer full
Allocate CPU time
-Time sharing
Indicate abnormal event(aCPU originates for notification and recovery)
-Illegal operation, hardware error
Software Interrupts
Servicing the interrupt
Lower priority interrupts are held until higher priority interrupts are complete --> Suspend
program in progress --> Save context, including last instruction executed and data values in
registers, in the PCB or the stack area in memory --> Branch to interrupt handler program
Servicing the interrupt - Steps
1. Before interrupt arrives, program A is executing. The program counter points to the current
instruction
2. When the interrupt is received by the CPU, the current instruction is completed, all the
registers are saved in the stack area ( or in special area known as a process control block). The
PC is loaded with the starting location of program B, the interrupt handler program. This causes
a jump to program B, which becomes the executing program
3. When the interrupt routine is complete, the register are restored, including the program
counter, and the original program resumes exactly where it left off.
Direct Memory Access - Required conditions
-The I/O interface and memory must be connected
-The I/O controller must be capable of reading and writing to memory
-Conflicts between the CPu and the I/O controller must be avoided
-Interrupt required for completion
Basic Model of I/O
Processing speed or program execution
-Determined primarily by ability of I/O operations to stay ahead of processor
-Input --> Processor --> Output
I/O Requirements
1. Means for addressing different peripheral devices
2. A way for peripheral devices to initiate communication
with the CPU
3. An efficient means of transferring data directly between
I/O and memory for large data transfers since programmed I/O is suitable only for slow devices
and individual word transfers
4. Buses that interconnect high-speed I/O devices with the computer must support high data
transfer rates
5. Capability of handling devices operating at varying speeds with varying delays
6. Means for handling devices with extremely different control requirements
Peripherals
External devices what you connect to a computer (other than CPU, Power, memory)
Simple I/O configuration
CPU -> I/O Controller -> I/O device
,Northbridge
special chip to handle communication between CPU, GPU, and RAM
Southbridge
Special chip to handle communication between northbridge and interfaces such as the USB and
SATA (harddrive) interfaces
More Complex I/O Module, Intel Xeon
Separate IO controller chipes might have been present for Ethernet, Audio, if not part of
Southbridge
In the Intel Core Series
Northbridge is now a part of the CPU
Advanced I/O techniques - Programmed I/O
-CPU controlled I/O and CPU initiated
-I/O data and address registers in CPU
-one word transfer per I/O instruction
-Address information for each I/O device
-Full instruction fetch/execute cycle
--Used or keyboard and other communication with I/O controllers
Advanced I/O techniques - Interrupt Driven I/O
-External input controls
-CPU adopts whatever it wants
-Not CPU initiated
Advanced I/O techniques - Direct Memory Access Controllers
Method for transferring data between main memory and a device that bypasses the CPU
Programmed I/O example
,see docs
Accumulator
where the CPU does its scratch work, in the ALU
Interrupts in the CPU
-Signal that causes the CPU to alter its normal flow of instruction execution
-Frees CPU from waiting for events
-Provides control for external I/O initiation
Interrupts in the CPU - examples
-Unexpected input
-Abnormal situation
-Illegal situations
-Multitasking, multiprocessing
Interrupt Teminology - Interrupt lines
Hardware on one mor more special control lines to the CPU
Interrupt Terminology - Interrupt request
see docs
Interrupt Terminology - Interrupt handlers
-Program that services the interrupt
-Also known as an interrupt routine or device driver
Interrupt Terminology - Context
-Saved registers of a program before control is transferred to the interrupt handler
-Allows program to resume exactly where it left over when control returns to interrupted
program
Use of Interrupts
, Notify that an external event has occurred
- Real or time sensitive
Signal Completion
-Printer ready or buffer full
Allocate CPU time
-Time sharing
Indicate abnormal event(aCPU originates for notification and recovery)
-Illegal operation, hardware error
Software Interrupts
Servicing the interrupt
Lower priority interrupts are held until higher priority interrupts are complete --> Suspend
program in progress --> Save context, including last instruction executed and data values in
registers, in the PCB or the stack area in memory --> Branch to interrupt handler program
Servicing the interrupt - Steps
1. Before interrupt arrives, program A is executing. The program counter points to the current
instruction
2. When the interrupt is received by the CPU, the current instruction is completed, all the
registers are saved in the stack area ( or in special area known as a process control block). The
PC is loaded with the starting location of program B, the interrupt handler program. This causes
a jump to program B, which becomes the executing program
3. When the interrupt routine is complete, the register are restored, including the program
counter, and the original program resumes exactly where it left off.
