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Digital Logic Design (DLD) Test QUESTIONS with 100% Correct Answers Already Passed

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Digital Logic Design (DLD) Test QUESTIONS with 100% Correct Answers Already Passed

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Digital Logic Design
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Uploaded on
November 29, 2024
Number of pages
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Written in
2024/2025
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Digital Logic Design (DLD) Test QUESTIONS with
100% Correct Answers Already Passed

A system is a structure that is guaranteed to exhibit _______, assuming all of its components
obey their specified behaviors. - ✔✔a specified behavior


What maintains the obligations and responsibilities of every system component? -
✔✔contracts



How do we implement devices with high reliability? - ✔✔We use a representation
convention that forbids a range of voltages between 0 and 1



A combinational device is a circuit element that has: - ✔✔1. one or more digital inputs
2. one or more digital outputs
3. a functional specification



Can a combinational device contain directed cycles?(Yes/no) - ✔✔No



Does a wire obey the static discipline? (yes/no) - ✔✔No



What are sources of power supply noise? - ✔✔IR drop
L(dl/dt) drop



What must accept marginal inputs and provide unquestionable outputs? - ✔✔Combinational
device



What does the VTC acronym mean? - ✔✔Voltage Transfer Characteristic

, The VTC of a buffer is: - ✔✔nonlinear and with a gain > 1



The VTC measures: - ✔✔static behavior



If we design a system with lots of gain, what will that buy us? - ✔✔a big noise margin


Current flows between the diffusion terminals in a MOSFET if the voltage on the gate terminal
is large enough to create a conducting "channel", otherwise the MOSFET is off and the diffusion
terminals are not connected.(T/F) - ✔✔True



What are the four terminals of a Field Effect Transitor? - ✔✔gate, source, drain, and bulk



You should only use PFETs in what kind of circuits? - ✔✔pullup


We want _________ pullup and pulldown logic, i.e., the pulldown should be on when the pulp
is off and vice versa. - ✔✔complementary


In the general CMOS gate recipe, the output node is always a low-impedance node in the
steady state.(T/F) - ✔✔True


If there is no change in value from input to output through a circuit, then the process takes zero
time. (T/F) - ✔✔False



What kind of bound is had on the delay from valid inputs to valid outputs? - ✔✔upper



[A] delay is a [B] bound on the delay from any invalid input to an invalid output. - ✔✔[A]
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