CPEN Practice Exam TEST MOD 014 with Actual Questions &
Answers 2023/2024
Op Code correct answers The portion of a machine language instruction that specifies the operation to
be done by the CPU
μPC correct answers This keeps track of the location of the next microword to be retrieved from
microcode storage
EPIC correct answers The "architecture technology" used in Intel's IA-64 (Itanium family) chips
Booth's Algorithm correct answers This can be used to efficiently multiply signed integers
Pipeline Register correct answers This is used to separate one stage of a pipeline from the next
Wallace tree correct answers A structure comprised of multiple levels of carry save adders
Positive Infinity correct answers This is the result when the operation +1.0/0.0 is performed on a system
with IEEE-754 floating-point arithmetic
Negative Infinity correct answers This is the result when the operation -1.0/0.0 is performed on a system
with IEEE-754 floating-point arithmetic
Motorola 68000 correct answers This CISC microprocessor had 16 programmer-visible registers and was
used in the original, 1980s Apple Macintosh computers
One-operand Instructions correct answers These would be characteristic of an accumulator-based
instruction set
Vertical Microprogramming correct answers A technique used to reduce the size of microprogram
memory by encoding the bit fields to represent mutually exclusive control signals
Delayed Branch correct answers A technique used in pipelined CPUs where the instruction immediately
following a control transfer instruction is executed as though it came before the control transfer
Superscalar Architectue correct answers A type of architecture that uses multiple, pipelined instruction
execution units with resolution of inter-instruction dependencies done at run time by the machine's
control unit
Which of these circuits would be most specifically useful in constructing a "Wallace tree" binary
multiplier? correct answers Carry Save Adder
In which of the following respects is a typical RISC processor at a disadvantage with respect to a CISC
processor? correct answers Code Size
Answers 2023/2024
Op Code correct answers The portion of a machine language instruction that specifies the operation to
be done by the CPU
μPC correct answers This keeps track of the location of the next microword to be retrieved from
microcode storage
EPIC correct answers The "architecture technology" used in Intel's IA-64 (Itanium family) chips
Booth's Algorithm correct answers This can be used to efficiently multiply signed integers
Pipeline Register correct answers This is used to separate one stage of a pipeline from the next
Wallace tree correct answers A structure comprised of multiple levels of carry save adders
Positive Infinity correct answers This is the result when the operation +1.0/0.0 is performed on a system
with IEEE-754 floating-point arithmetic
Negative Infinity correct answers This is the result when the operation -1.0/0.0 is performed on a system
with IEEE-754 floating-point arithmetic
Motorola 68000 correct answers This CISC microprocessor had 16 programmer-visible registers and was
used in the original, 1980s Apple Macintosh computers
One-operand Instructions correct answers These would be characteristic of an accumulator-based
instruction set
Vertical Microprogramming correct answers A technique used to reduce the size of microprogram
memory by encoding the bit fields to represent mutually exclusive control signals
Delayed Branch correct answers A technique used in pipelined CPUs where the instruction immediately
following a control transfer instruction is executed as though it came before the control transfer
Superscalar Architectue correct answers A type of architecture that uses multiple, pipelined instruction
execution units with resolution of inter-instruction dependencies done at run time by the machine's
control unit
Which of these circuits would be most specifically useful in constructing a "Wallace tree" binary
multiplier? correct answers Carry Save Adder
In which of the following respects is a typical RISC processor at a disadvantage with respect to a CISC
processor? correct answers Code Size
