CEA FINAL EXAM STUDY GUIDE 2025/2026 COMPLETE QUESTIONS WITH VERIFIED CORRECT SOLUTIONS || 100% GUARANTEED PASS <RECENT VERSION>

CEA FINAL EXAM STUDY GUIDE 2025/2026 COMPLETE QUESTIONS WITH VERIFIED CORRECT SOLUTIONS || 100% GUARANTEED PASS &lt;RECENT VERSION&gt; 1. The _________ contains logic for performing a communication function between the peripheral and the bus. a. I/O channel b. I/O module c. I/O processor d. I/O command - ANSWER B 2. The most common means of computer/user interaction is a __________. a. keyboard/monitor b. mouse/printer c. modem/printer d. monitor/printer - ANSWER A 3. The I/O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices. a. cycle b. status reporting c. control and timing d. data - ANSWER C 4. An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually referred to as an _________. a. I/O channel b. I/O command c. I/O controller d. device controller - ANSWER A 5. An I/O module that is quite primitive and requires detailed control is usually referred to as an _________. a. I/O command b. I/O controller c. I/O channel d. I/O processor - ANSWER B 6. The _________ command causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral. a. control b. test c. read d. write - ANSWER D 7. The ________ command is used to activate a peripheral and tell it what to do. a. control b. test c. read d. write - ANSWER A 8. ________ is when the DMA module must force the processor to suspend operation temporarily. a. Interrupt b. Thunderbolt c. Cycle stealing d. Lock down - ANSWER C 9. The 8237 DMA is known as a _________ DMA controller. a. command b. cycle stealing c. interrupt d. fly-by - ANSWER D 10. ________ is a digital display interface standard now widely adopted for computer monitors, laptop displays, and other graphics and video interfaces. a. DisplayPort b. PCI Express c. Thunderbolt d. InfiniBand - ANSWER A 11. The ________ layer is the key to the operation of Thunderbolt and what makes it attractive as a high-speed peripheral I/O technology. a. cable b. application c. common transport d. physical - ANSWER C 12. The Thunderbolt protocol _________ layer is responsible for link maintenance including hot-plug detection and data encoding to provide highly efficient data transfer. a. cable b. application c. common transport d. physical - ANSWER D 13. The ________ contains I/O protocols that are mapped on to the transport layer. a. cable b. application c. common transport d. physical - ANSWER B 14. A ________ is used to connect storage systems, routers, and other peripheral devices to an InfiniBand switch. a. target channel adapter b. InfiniBand switch c. host channel adapter d. subnet - ANSWER A 15. A ________ connects InfiniBand subnets, or connects an InfiniBand switch to a network such as a local area network, wide area network, or storage area network. a. memory controller b. TCA c. HCA d. router - ANSWER D 16. . With ________ instructions are simultaneously issued from multiple threads to the execution units of a superscalar processor. A. SMT B. Single-threaded scalar C. Coarse-grained multithreading D. Chip multiprocessing - ANSWER A 17. Replicating the entire processor on a single chip with each processor handling separate threads is ________. A. Interleaved multithreading Blocked multithreading C. Simultaneous multithreading D. Chip multiprocessing - ANSWER D 18. Which representation is most efficient to perform arithmetic operations on the numbers? A. Sign-magnitude B. 1's complement C. 2's complement D. None of the others - ANSWER C 19. When we perform the addition on -7 and 1 the answer in 2's complement form is ________. A. 1010 B. 1110 C. 0110 D. 1000 - ANSWER A 20. When we perform the multiplication on 110101 and 1111 the result of the operation is ________. A. B. C. D. - ANSWER A 21. When 1101 is used to divide 1110110 the remainder is ______ . A. 0 B. 1 C. 10 D. 100 - ANSWER B 22. . ________ registers enable the machine or assembly language programmer to minimize main memory references by optimizing use of registers. A. General purpose B. Control and status C. User-visible D. None of the others - ANSWER C 23. Which register of the following connects to the address bus directly? A. PC B. MAR C. MBR D. None of the others - ANSWER B 24. Addressing mode used in instruction SUB r1, r2 is ________. A. Immediate B. Indirect C. Base D. Register - ANSWER D 25. In immediate addressing mode the operand is placed ________. A. In the CPU register B. After OP code in the instruction C. In memory D. In stack - ANSWER B 26. How many address lines are needed to address each memory location in a 2048 X 4 memory chip? A. 10 B. 11 C. 8 D. 12 - ANSWER B 27. A processor performing fetch or decoding of different instruction during the execution of another instruction is called ______ . A. Super-scaling B. Pipe-lining C. Parallel Computation D. None of the others - ANSWER B 28. The periods of time when the pipeline, or some portion of the pipeline, is idle is called as _____. A. Hazards B. Stalls C. Bubbles D. Stalls or Bubbles - ANSWER D 29. Which computer architecture aimed at reducing the number of instructions per program? A. CISC B. RISC C. ISA D. ANNA - ANSWER A 30. Which computer architecture aimed at reducing the time of execution of instructions? A. ANNA B. RISC C. CISC D. ISA - ANSWER B 31. Which computer architecture was the first to implement pipe-lining? A. ISA B. CISC C. RISC D. ANNA - ANSWER C 32. . The Sun microsystems processors usually follow ________ architecture. A. CISC B. ISA C. ULTRA SPARC D. RISC - ANSWER D 33. Which of the following is typical distinguishing characteristics of RISC organization? A. A limited instruction set with a fixed format B. A large number of registers or the use of a compiler that optimizer register usage C. An emphasis on optimizing the instruction pipeline D. All of the others - ANSWER D 34. Both CISC and RISC architectures have been developed to minimize what? A. Cost B. Time delay C. Semantic gap D. All of the others - ANSWER C - Statement I : The major cost in the life cycle of a system is hardware. - 35. Statement II : Almost all RISC instructions use simple register addressing. Which of the above statements are true? A. Both the statements are true B. Statement I is true C. Statement II is true D. Both the statements are false - ANSWER C 36. ________ is a way of increasing the efficiency of the pipeline by making use of a branch that does not take effect until after execution of the following instruction. A. Delayed branch B. Delayed load C. Unrolling D. None of the others - ANSWER A 37. ________ can improve performance by reducing loop overhead, increasing instruction parallelism by improving pipeline performance, and improving register, data cache, or TLB locality. A. Delayed branch B. Delayed load C. Unrolling D. None of the others - ANSWER C 38. 21. ________ is the fastest available storage device. A. Main memory B. Cache C. Register storage D. HLLs - ANSWER C 39. The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines. A. Scalar B. Branch C. Superscalar D. Flow dependency - ANSWER C 40. Which of the following is a fundamental limitation to parallelism with which the system must cope? A. Procedural dependency B. Resource conflicts C. Anti-dependency D. All of the others - ANSWER D 41. The situation where the second instruction needs data produced by the first instruction to execute is referred to as __________. A. True data dependency B. Output dependency C. Procedural dependency D. Anti-dependency - ANSWER A 42. The instructions following a branch have a _________ on the branch and cannot be executed until the branch is executed. A. Anti-dependency B. Procedural dependency C. Output dependency D. True data dependency - ANSWER B 43. ________ refers to the process of initiating instruction execution in the processor's functional units. A. Instruction issue B. In-order issue C. Out-of-order issue D. Procedural issue - ANSWER A 44. Instead of the first instruction producing a value that the second instruction uses, with ___________ the second instruction destroys a value that the first instruction uses. A. In-order issue B. Resource conflict C. Anti-dependency D. Out-of-order completion - ANSWER C 45. __________ exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping. A. Flow dependency B. Instruction-level parallelism C. Machine parallelism D. Instruction issue - ANSWER B 46. _________ is determined by the number of instructions that can be fetched and executed at the same time and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions. A. Machine parallelism B. Instruction-level parallelism C. Output dependency D. Procedural dependency - ANSWER A 47. Which of the following is a hardware technique that can be used in a superscalar processor to enhance performance? A. duplication of resources B. out-of-order issue C. renaming D. all of the others - ANSWER D 48. Microprocessors that are used for one particular job are classified as A. Dedicated microprocessors B. Dedicated computers C. Dedicated microcomputers D. Dedicated mega computers - ANSWER A 49. . At the integrated circuit level, what are the three principal constituents of a computer system? A. Wafers, chips, and interconnections among them B. Chips, memory cells, and interconnections among them C. Gates, memory cells, and interconnections among them D. None of the others - ANSWER C 50. CISC stands for ... A. Complete Instruction Sequential Compilation B. Computer Integrated Sequential Compiler C. Complex Instruction Set Computer D. Complex Instruction Sequential Compilation - ANSWER 51. Which types of programmers should be aware of instruction set architecture? (Select all correct answers) A. Application Programmer B. System Programmer C. Compiler Designer D. HLL Programmers - ANSWER B,C 52. Compact discs, (according to the original CD specifications) hold how many minutes of music? A. 74 mins B. 56 mins C. 60 mins D. 90 mins - ANSWER A 53. During the execution of a program which gets initialized first? A. MBR B. IR C. PC D. MAR - ANSWER C 54. The fetch and execution cycles are interleaved with the help of ... A. Modification in processor architecture B. Clock C. Special unit D. Control unit - ANSWER B 55. Any computer must at least consist of: A. Data bus B. Address bus C. Control bus D. All of the others - ANSWER D 56. The main virtue &lt;ưu điểm, tính hấp dẫn, ...&gt; for using single bus structure is: A. Fast data transfers B. Cost effective connectivity and speed C. Cost effective connectivity and ease of attaching peripheral devices D. None of the others - ANSWER C 57. 10. To extend the connectivity of the processor bus we use ... A. PCI bus B. SCSI bus C. Controllers D.Multiple bus - ANSWER A 58. PCI stands for ... A. Peripheral Component Interconnect B. Peripheral Computer Interconnect C. Peripheral Component In circuit D. None of the others - ANSWER A 59. Memory system of computers includes: A. Cache, External Memory B. External Memory, ROM C. Optical Disk, Internal Memory D. Internal Memory, External Memory - ANSWER D 60. A USB pipe is a ______ channel. a) Simplex b) Half-Duplex c) Full-Duplex d) Both Simplex and Full-Duplex - ANSWER c