Fetch decode execute
compiler hastodo more workto compiler has less w
Address from the PC is copiedintothe MAR translate highlevel to machine code high level rode into mac
bus tomainmemorywhere it waitsfor
1 a
pen
Iff More RAM is required
code
to store the Less RAM is required sin
instruc
Controlunitsends read signal on controlbus to main
memory Manyspecialised
Contents
can now be senton databus to thememorydataregister Pipelining is possible since each even though only a fe
MDRcopies into CIR instruction takes one clock gate used
DC gets incremented
processor whichhaslots of independent working in parallel
iii ii s.it i
Multi core CPUshave multiple independent
cores thatcan complete
instructions separately which results in higher performance
nd addressto the MAR
sendaddress down addressbus to main Parallel accomplish a similar task as
memory they use threading
CU readsthe read signalalongcontrol bus In larger projects multicore performbetter
Contents stored at address canbesent
alongdatabustoMDR
MDRcopied into ACC
instruction is complete
RAM fast volatile temporystorage optical devices are read from andwr
cannotbe modified bootstrap BTaginformation is
ROM represented
by
nonvolatile reflect or scatter the light
virtual storage storinginformation remotely Pits 0
lands
CDs DVDs Blu
each
so can beaccessed
computer
byany
is highcost
elining process of completing the fde cycle of 3
formation
separate instructions simultaneously magnetically represent
polarisedand unpolarised
, 2 Interrupt Service routine
collection of thatwork together
perating system programs
checks the content of the interrupt register atthe end of
to provide an interface between the user
each fde cycle
and computer
current contents of the special purpose
registers in the
OS provides the followingfeatures
CPO are temporarily transferedinto a stack
memory management
loads appropriate ISR into RAM
resource management
file management
Scheduling
input output management
Software
utility Jobs receive a fair amount of processingtime
security
1 preemptive
UI
Jobs are activelymade to start stopbytheOS
MLFQ SRT RR
Ty ages
is split up into equal size sections known as
2 non preemptive
once a job is started it is left fill it is completed
ÉI
FCFS SSF
upof memoryinto logical sizeddivisions known as
segments
typesofos to
low the structure and logical flow of the program
Distributed run across multiple devices
memoy
compiler hastodo more workto compiler has less w
Address from the PC is copiedintothe MAR translate highlevel to machine code high level rode into mac
bus tomainmemorywhere it waitsfor
1 a
pen
Iff More RAM is required
code
to store the Less RAM is required sin
instruc
Controlunitsends read signal on controlbus to main
memory Manyspecialised
Contents
can now be senton databus to thememorydataregister Pipelining is possible since each even though only a fe
MDRcopies into CIR instruction takes one clock gate used
DC gets incremented
processor whichhaslots of independent working in parallel
iii ii s.it i
Multi core CPUshave multiple independent
cores thatcan complete
instructions separately which results in higher performance
nd addressto the MAR
sendaddress down addressbus to main Parallel accomplish a similar task as
memory they use threading
CU readsthe read signalalongcontrol bus In larger projects multicore performbetter
Contents stored at address canbesent
alongdatabustoMDR
MDRcopied into ACC
instruction is complete
RAM fast volatile temporystorage optical devices are read from andwr
cannotbe modified bootstrap BTaginformation is
ROM represented
by
nonvolatile reflect or scatter the light
virtual storage storinginformation remotely Pits 0
lands
CDs DVDs Blu
each
so can beaccessed
computer
byany
is highcost
elining process of completing the fde cycle of 3
formation
separate instructions simultaneously magnetically represent
polarisedand unpolarised
, 2 Interrupt Service routine
collection of thatwork together
perating system programs
checks the content of the interrupt register atthe end of
to provide an interface between the user
each fde cycle
and computer
current contents of the special purpose
registers in the
OS provides the followingfeatures
CPO are temporarily transferedinto a stack
memory management
loads appropriate ISR into RAM
resource management
file management
Scheduling
input output management
Software
utility Jobs receive a fair amount of processingtime
security
1 preemptive
UI
Jobs are activelymade to start stopbytheOS
MLFQ SRT RR
Ty ages
is split up into equal size sections known as
2 non preemptive
once a job is started it is left fill it is completed
ÉI
FCFS SSF
upof memoryinto logical sizeddivisions known as
segments
typesofos to
low the structure and logical flow of the program
Distributed run across multiple devices
memoy
