Solutions Manual
Digital Design with an Introduction to the Verilog HDL VHDL
and System Verilog
By. Morris Mano
6th Edition
2
,CHAPTER 1
1.1 Base-10: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Octal: 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 40
Hex: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
Base-12 14 15 16 17 18 19 1A 1B 20 21 22 23 24 25 26 27 28
1.2 (A) 32,768 (B) 67,108,864 (C) 6,871,947,674
3 2 1
1.3 (4310)5 = 4 * 5 + 3 * 5 + 1 * 5 = 58010
(198)12 = 1 * 122 + 9 * 121 + 8 * 120 = 26010
(435)8 = 4 * 82 + 3 * 81 + 5 * 80 = 28510
(345)6 = 3 * 62 + 4 * 61 + 5 * 60 = 13710
1.4 16-Bit Binary: 1111_1111_1111_1111
Decimal Equivalent: 216 -1 = 65,53510
Hexadecimal Equivalent: FFFF16
1.5 Let B = Base
(A) 14/2 = (B + 4)/2 = 5, So B = 6
(B) 54/4 = (5*B + 4)/4 = B + 3, So 5 * B = 52 – 4, And B = 8
(C) (2 *B + 4) + (B + 7) = 4b, So B = 11
1.6 (X – 3)(X – 6) = X2 –(6 + 3)X + 6*3 = X2 -11x + 22
Therefore: 6 + 3 = B + 1m, So B = 8
Also, 6*3 = (18)10 = (22)8
1.7 64CD16 = 0110_0100_1100_1101 2 = 110_010_011_001 _101 = (62315 )8
1.8 (A) Results Of Repeated Division By 2 (Quotients Are Followed By Remainders):
43110 = 215(1); 107(1); 53(1); 26(1); 13(0); 6(1) 3(0) 1(1)
Answer: 1111_10102 = FA16
(B) Results Of Repeated Division By 16:
43110 = 26(15); 1(10)
(Faster) Answer: FA =
1111_1010
1.9 (A) 10110.01012 = 16 + 4 + 2 + .25 + .0625 = 22.3125
(B) 16.516 = 16 + 6 + 5*(.0615) = 22.3125
(C) 26.248 = 2 * 8 + 6 + 2/8 + 4/64 = 22.3125
(D) DADA.B16 = 14*163 + 10*162 + 14*16 + 10 + 11/16 = 60,138.6875
Digital Design With An Introduction To The Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright
2012, All Rights Reserved.
, 3
(E) 1010.11012 = 8 + 2 + .5 + .25 + .0625 = 10.8125
1.10 (A) 1.100102 = 0001.10012 = 1.916 = 1 + 9/16 = 1.56310
(B) 110.0102 = 0110.01002 = 6.416 = 6 + 4/16 = 6.2510
Reason: 110.0102 Is The Same As 1.100102 Shifted To The Left By Two Places.
1011.11
1.11 101 | 111011.0000
101
01001
101
1001
101
1000
101
0110
The Quotient Is Carried To Two Decimal Places, Giving
1011.11
Checking: = ≅ 1011.112 = 58.7510
1.12 (A) 10000 And 110111
1011 1011
+101 X101
10000 = 1610 1011
1011
110111 = 5510
(B) 62h And
958h
2Eh 0010_1110 2Eh
+34 H 0011_0100 X34h
62h 0110_0010 = 9810 B38
82A
9 5 8h = 239210
1.13 (A) Convert 27.315 To Binary:
Integer Remainder Coefficient
Quotient
27/2 = 13 + ½ A0 = 1
13/2 6 + ½ A1 = 1
6/2 3 + 0 A2 = 0
3/2 1 + ½ A3 = 1
½ 0 + ½ A4 = 1
Digital Design With An Introduction To The Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright
2012, All Rights Reserved.
, 4
2710 = 110112
Integer Fraction Coefficient
.315 X 2 = 0 + .630 A-1 = 0
.630 X 2 = 1 + .26 A-2 = 1
.26 X 2 = 0 + .52 A-3 = 0
.52 X 2 = 1 + .04 A-4 = 1
.31510 ≅ .01012 = .25 + .0625 = .3125
27.315 ≅ 11011.01012
(B) 2/3 ≅ .6666666667
Integer Fraction Coefficient
.6666_6666_67 X 2 = 1 + .3333_3333_34 A-1 =
.3333333334 X 2 = 0 + .6666666668 1 -2 =
A
.6666666668 X 2 = 1 + .3333333336 0 -3 =
A
.3333333336 X 2 = 0 + .6666666672 1A-4 =
.6666666672 X 2 = 1 + .3333333344 0 -5 =
A
.3333333344 X 2 = 0 + .6666666688 1 -6 =
A
.6666666688 X 2 = 1 + .3333333376 0 -7 =
A
.3333333376 X 2 = 0 + .6666666752 1A-8 =
0
.666666666710 ≅ .101010102 = .5 + .125 + .0313 + ..0078 = .664110
.101010102 = .1010_10102 = .AA16 = 10/16 + 10/256 = .664110 (Same As (B)).
1.14 (A) 0001_0000 (B) 0000_0000 (C)
1101_1010
1s Comp: 1110_1111 1s Comp: 1111_1111 1s Comp: 0010_0101
2s Comp: 1111_0000 2s Comp: 0000_0000 2s Comp: 0010_0110
(D) 1010_1010 (E) 1000_0101 (F) 1111_1111
1s Comp: 0101_0101 1s Comp: 0111_1010 1s Comp: 0000_0000
2s Comp: 0101_0110 2s Comp: 0111_1011 2s Comp: 0000_0001
`
1.15 (A) 25,478,036 (B) 63,325,600
9s Comp: 74,521,963 9s Comp: 36,674,399
10s Comp: 74,521,964 10s Comp: 36,674,400
(C) 25,000,000 (D) 00000000
9s Comp: 74,999,999 9s Comp: 99999999
10s Comp: 75,000,000 10s Comp: 100000000
1.16 C3DF C3DF: 1100_0011_1101_1111
15s Comp: 3C20 1s Comp: 0011_1100_0010_0000
16s Comp: 3C21 2s Comp: 0011_1100_0010_0001 = 3C21
1.17 (A) 2,579 → 02,579 →97,420 (9s Comp) → 97,421 (10s Comp)
4637 – 2,579 = 2,579 + 97,421 = 205810
(B) 1800 → 01800 → 98199 (9s Comp) → 98200 (10
Comp)
125 – 1800 = 00125 + 98200 = 98325
(Negative) Magnitude: 1675
Result: 125 – 1800 = 1675
Digital Design With An Introduction To The Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright
2012, All Rights Reserved.
Digital Design with an Introduction to the Verilog HDL VHDL
and System Verilog
By. Morris Mano
6th Edition
2
,CHAPTER 1
1.1 Base-10: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Octal: 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 40
Hex: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
Base-12 14 15 16 17 18 19 1A 1B 20 21 22 23 24 25 26 27 28
1.2 (A) 32,768 (B) 67,108,864 (C) 6,871,947,674
3 2 1
1.3 (4310)5 = 4 * 5 + 3 * 5 + 1 * 5 = 58010
(198)12 = 1 * 122 + 9 * 121 + 8 * 120 = 26010
(435)8 = 4 * 82 + 3 * 81 + 5 * 80 = 28510
(345)6 = 3 * 62 + 4 * 61 + 5 * 60 = 13710
1.4 16-Bit Binary: 1111_1111_1111_1111
Decimal Equivalent: 216 -1 = 65,53510
Hexadecimal Equivalent: FFFF16
1.5 Let B = Base
(A) 14/2 = (B + 4)/2 = 5, So B = 6
(B) 54/4 = (5*B + 4)/4 = B + 3, So 5 * B = 52 – 4, And B = 8
(C) (2 *B + 4) + (B + 7) = 4b, So B = 11
1.6 (X – 3)(X – 6) = X2 –(6 + 3)X + 6*3 = X2 -11x + 22
Therefore: 6 + 3 = B + 1m, So B = 8
Also, 6*3 = (18)10 = (22)8
1.7 64CD16 = 0110_0100_1100_1101 2 = 110_010_011_001 _101 = (62315 )8
1.8 (A) Results Of Repeated Division By 2 (Quotients Are Followed By Remainders):
43110 = 215(1); 107(1); 53(1); 26(1); 13(0); 6(1) 3(0) 1(1)
Answer: 1111_10102 = FA16
(B) Results Of Repeated Division By 16:
43110 = 26(15); 1(10)
(Faster) Answer: FA =
1111_1010
1.9 (A) 10110.01012 = 16 + 4 + 2 + .25 + .0625 = 22.3125
(B) 16.516 = 16 + 6 + 5*(.0615) = 22.3125
(C) 26.248 = 2 * 8 + 6 + 2/8 + 4/64 = 22.3125
(D) DADA.B16 = 14*163 + 10*162 + 14*16 + 10 + 11/16 = 60,138.6875
Digital Design With An Introduction To The Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright
2012, All Rights Reserved.
, 3
(E) 1010.11012 = 8 + 2 + .5 + .25 + .0625 = 10.8125
1.10 (A) 1.100102 = 0001.10012 = 1.916 = 1 + 9/16 = 1.56310
(B) 110.0102 = 0110.01002 = 6.416 = 6 + 4/16 = 6.2510
Reason: 110.0102 Is The Same As 1.100102 Shifted To The Left By Two Places.
1011.11
1.11 101 | 111011.0000
101
01001
101
1001
101
1000
101
0110
The Quotient Is Carried To Two Decimal Places, Giving
1011.11
Checking: = ≅ 1011.112 = 58.7510
1.12 (A) 10000 And 110111
1011 1011
+101 X101
10000 = 1610 1011
1011
110111 = 5510
(B) 62h And
958h
2Eh 0010_1110 2Eh
+34 H 0011_0100 X34h
62h 0110_0010 = 9810 B38
82A
9 5 8h = 239210
1.13 (A) Convert 27.315 To Binary:
Integer Remainder Coefficient
Quotient
27/2 = 13 + ½ A0 = 1
13/2 6 + ½ A1 = 1
6/2 3 + 0 A2 = 0
3/2 1 + ½ A3 = 1
½ 0 + ½ A4 = 1
Digital Design With An Introduction To The Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright
2012, All Rights Reserved.
, 4
2710 = 110112
Integer Fraction Coefficient
.315 X 2 = 0 + .630 A-1 = 0
.630 X 2 = 1 + .26 A-2 = 1
.26 X 2 = 0 + .52 A-3 = 0
.52 X 2 = 1 + .04 A-4 = 1
.31510 ≅ .01012 = .25 + .0625 = .3125
27.315 ≅ 11011.01012
(B) 2/3 ≅ .6666666667
Integer Fraction Coefficient
.6666_6666_67 X 2 = 1 + .3333_3333_34 A-1 =
.3333333334 X 2 = 0 + .6666666668 1 -2 =
A
.6666666668 X 2 = 1 + .3333333336 0 -3 =
A
.3333333336 X 2 = 0 + .6666666672 1A-4 =
.6666666672 X 2 = 1 + .3333333344 0 -5 =
A
.3333333344 X 2 = 0 + .6666666688 1 -6 =
A
.6666666688 X 2 = 1 + .3333333376 0 -7 =
A
.3333333376 X 2 = 0 + .6666666752 1A-8 =
0
.666666666710 ≅ .101010102 = .5 + .125 + .0313 + ..0078 = .664110
.101010102 = .1010_10102 = .AA16 = 10/16 + 10/256 = .664110 (Same As (B)).
1.14 (A) 0001_0000 (B) 0000_0000 (C)
1101_1010
1s Comp: 1110_1111 1s Comp: 1111_1111 1s Comp: 0010_0101
2s Comp: 1111_0000 2s Comp: 0000_0000 2s Comp: 0010_0110
(D) 1010_1010 (E) 1000_0101 (F) 1111_1111
1s Comp: 0101_0101 1s Comp: 0111_1010 1s Comp: 0000_0000
2s Comp: 0101_0110 2s Comp: 0111_1011 2s Comp: 0000_0001
`
1.15 (A) 25,478,036 (B) 63,325,600
9s Comp: 74,521,963 9s Comp: 36,674,399
10s Comp: 74,521,964 10s Comp: 36,674,400
(C) 25,000,000 (D) 00000000
9s Comp: 74,999,999 9s Comp: 99999999
10s Comp: 75,000,000 10s Comp: 100000000
1.16 C3DF C3DF: 1100_0011_1101_1111
15s Comp: 3C20 1s Comp: 0011_1100_0010_0000
16s Comp: 3C21 2s Comp: 0011_1100_0010_0001 = 3C21
1.17 (A) 2,579 → 02,579 →97,420 (9s Comp) → 97,421 (10s Comp)
4637 – 2,579 = 2,579 + 97,421 = 205810
(B) 1800 → 01800 → 98199 (9s Comp) → 98200 (10
Comp)
125 – 1800 = 00125 + 98200 = 98325
(Negative) Magnitude: 1675
Result: 125 – 1800 = 1675
Digital Design With An Introduction To The Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright
2012, All Rights Reserved.
